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Commit b2d70917 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: properly handle cg on asics without UVD 



Don't try and enable clockgating if the asic doesn't have
UVD.  Use rdev->has_uvd rather than using local checks.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 46348dc2

drivers/gpu/drm/radeon/si.c

+2 −6
Original line number Diff line number Diff line
@@ -5215,14 +5215,12 @@ static void si_enable_mc_ls(struct radeon_device *rdev, 


static void si_init_cg(struct radeon_device *rdev)

{

	bool has_uvd = true;



	si_enable_mgcg(rdev, true);

	si_enable_cgcg(rdev, true);

	/* disable MC LS on Tahiti */

	if (rdev->family == CHIP_TAHITI)

		si_enable_mc_ls(rdev, false);

	if (has_uvd) {

	if (rdev->has_uvd) {

		si_enable_uvd_mgcg(rdev, true);

		si_init_uvd_internal_cg(rdev);

	}
@@ -5230,9 +5228,7 @@ static void si_init_cg(struct radeon_device *rdev) 


static void si_fini_cg(struct radeon_device *rdev)

{

	bool has_uvd = true;



	if (has_uvd)

	if (rdev->has_uvd)

		si_enable_uvd_mgcg(rdev, false);

	si_enable_cgcg(rdev, false);

	si_enable_mgcg(rdev, false);