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Commit b26ea06b authored by Thierry Reding's avatar Thierry Reding
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ARM: tegra: Add memory controller support for Tegra124



Add the memory controller and wire up the interrupt that is used to
report errors. Provide a reference to the memory controller clock and
mark the device as being an IOMMU by adding an #iommu-cells property.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c6f70a4d
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+11 −0
Original line number Diff line number Diff line
@@ -552,6 +552,17 @@
		reset-names = "fuse";
	};

	mc: memory-controller@0,70019000 {
		compatible = "nvidia,tegra124-mc";
		reg = <0x0 0x70019000 0x0 0x1000>;
		clocks = <&tegra_car TEGRA124_CLK_MC>;
		clock-names = "mc";

		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;
	};

	sata@0,70020000 {
		compatible = "nvidia,tegra124-ahci";