Loading drivers/spi/spi-geni-qcom.c +14 −11 Original line number Diff line number Diff line Loading @@ -356,9 +356,6 @@ static struct msm_gpi_tre *setup_config0_tre(struct spi_transfer *xfer, if (mode & SPI_CPHA) flags |= GSI_CPHA; if (xfer->cs_change) flags |= GSI_CS_TOGGLE; word_len = xfer->bits_per_word - MIN_WORD_LEN; pack |= (GSI_TX_PACK_EN | GSI_RX_PACK_EN); ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div); Loading Loading @@ -586,8 +583,11 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, } cs |= spi_slv->chip_select; if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) if (!xfer->cs_change) { if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) go_flags |= FRAGMENTATION; } go_tre = setup_go_tre(cmd, cs, rx_len, go_flags, mas); sg_init_table(xfer_tx_sg, tx_nent); Loading Loading @@ -940,8 +940,6 @@ static void setup_fifo_xfer(struct spi_transfer *xfer, m_cmd = SPI_RX_ONLY; spi_tx_cfg &= ~CS_TOGGLE; if (xfer->cs_change) spi_tx_cfg |= CS_TOGGLE; if (!(mas->cur_word_len % MIN_WORD_LEN)) { trans_len = ((xfer->len << 3) / mas->cur_word_len) & TRANS_LEN_MSK; Loading @@ -950,8 +948,12 @@ static void setup_fifo_xfer(struct spi_transfer *xfer, trans_len = (xfer->len / bytes_per_word) & TRANS_LEN_MSK; } if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) if (!xfer->cs_change) { if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) m_param |= FRAGMENTATION; } mas->cur_xfer = xfer; if (m_cmd & SPI_TX_ONLY) { Loading @@ -966,8 +968,9 @@ static void setup_fifo_xfer(struct spi_transfer *xfer, geni_write_reg(spi_tx_cfg, mas->base, SE_SPI_TRANS_CFG); geni_setup_m_cmd(mas->base, m_cmd, m_param); GENI_SE_DBG(mas->ipc, false, mas->dev, "%s: trans_len %d xferlen%d tx_cfg 0x%x cmd 0x%x\n", __func__, trans_len, xfer->len, spi_tx_cfg, m_cmd); "%s: trans_len %d xferlen%d tx_cfg 0x%x cmd 0x%x cs %d\n", __func__, trans_len, xfer->len, spi_tx_cfg, m_cmd, xfer->cs_change); if (m_cmd & SPI_TX_ONLY) geni_write_reg(mas->tx_wm, mas->base, SE_GENI_TX_WATERMARK_REG); /* Ensure all writes are done before the WM interrupt */ Loading Loading
drivers/spi/spi-geni-qcom.c +14 −11 Original line number Diff line number Diff line Loading @@ -356,9 +356,6 @@ static struct msm_gpi_tre *setup_config0_tre(struct spi_transfer *xfer, if (mode & SPI_CPHA) flags |= GSI_CPHA; if (xfer->cs_change) flags |= GSI_CS_TOGGLE; word_len = xfer->bits_per_word - MIN_WORD_LEN; pack |= (GSI_TX_PACK_EN | GSI_RX_PACK_EN); ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, &idx, &div); Loading Loading @@ -586,8 +583,11 @@ static int setup_gsi_xfer(struct spi_transfer *xfer, } cs |= spi_slv->chip_select; if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) if (!xfer->cs_change) { if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) go_flags |= FRAGMENTATION; } go_tre = setup_go_tre(cmd, cs, rx_len, go_flags, mas); sg_init_table(xfer_tx_sg, tx_nent); Loading Loading @@ -940,8 +940,6 @@ static void setup_fifo_xfer(struct spi_transfer *xfer, m_cmd = SPI_RX_ONLY; spi_tx_cfg &= ~CS_TOGGLE; if (xfer->cs_change) spi_tx_cfg |= CS_TOGGLE; if (!(mas->cur_word_len % MIN_WORD_LEN)) { trans_len = ((xfer->len << 3) / mas->cur_word_len) & TRANS_LEN_MSK; Loading @@ -950,8 +948,12 @@ static void setup_fifo_xfer(struct spi_transfer *xfer, trans_len = (xfer->len / bytes_per_word) & TRANS_LEN_MSK; } if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) if (!xfer->cs_change) { if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) m_param |= FRAGMENTATION; } mas->cur_xfer = xfer; if (m_cmd & SPI_TX_ONLY) { Loading @@ -966,8 +968,9 @@ static void setup_fifo_xfer(struct spi_transfer *xfer, geni_write_reg(spi_tx_cfg, mas->base, SE_SPI_TRANS_CFG); geni_setup_m_cmd(mas->base, m_cmd, m_param); GENI_SE_DBG(mas->ipc, false, mas->dev, "%s: trans_len %d xferlen%d tx_cfg 0x%x cmd 0x%x\n", __func__, trans_len, xfer->len, spi_tx_cfg, m_cmd); "%s: trans_len %d xferlen%d tx_cfg 0x%x cmd 0x%x cs %d\n", __func__, trans_len, xfer->len, spi_tx_cfg, m_cmd, xfer->cs_change); if (m_cmd & SPI_TX_ONLY) geni_write_reg(mas->tx_wm, mas->base, SE_GENI_TX_WATERMARK_REG); /* Ensure all writes are done before the WM interrupt */ Loading