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Commit b23feb08 authored by Karthikeyan Mani's avatar Karthikeyan Mani
Browse files

ARM: dts: msm: Enable tavil i2c mode on sdxpoorwills 



Update pictrl to enable i2c communication with
tavil. Add ion memory device tree entry to
allocate shared memory for pcm communication
between apps and modem.

Change-Id: I6cd88e921be0d7a9fa1c331516f2e501424af737
Signed-off-by: default avatarKarthikeyan Mani <kmani@codeaurora.org>
parent 6847aa66

arch/arm/boot/dts/qcom/sdxpoorwills-audio-overlay.dtsi

+9 −12
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ 


&snd_934x {

	qcom,audio-routing =

		"AIF4 VI", "MCLK",

		"RX_BIAS", "MCLK",

		"MADINPUT", "MCLK",

		"AMIC2", "MIC BIAS2",
@@ -28,8 +27,6 @@ 
		"MIC BIAS2", "ANCLeft Headset Mic",

		"AMIC5", "MIC BIAS3",

		"MIC BIAS3", "Handset Mic",

		"DMIC0", "MIC BIAS1",

		"MIC BIAS1", "Digital Mic0",

		"DMIC1", "MIC BIAS1",

		"MIC BIAS1", "Digital Mic1",

		"DMIC2", "MIC BIAS3",
@@ -40,14 +37,13 @@ 
		"MIC BIAS4", "Digital Mic4",

		"DMIC5", "MIC BIAS4",

		"MIC BIAS4", "Digital Mic5",

		"SpkrLeft IN", "SPK1 OUT",

		"SpkrRight IN", "SPK2 OUT";



	qcom,msm-mbhc-hphl-swh = <1>;

	qcom,msm-mbhc-gnd-swh = <1>;

	qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>;

	qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>;

	qcom,tavil-mclk-clk-freq = <12288000>;

	qcom,tavil-mclk-clk-freq = <9600000>;



	asoc-codec = <&stub_codec>;

	asoc-codec-names = "msm-stub-codec.1";
@@ -66,23 +62,24 @@ 
		interrupt-controller;

		#interrupt-cells = <1>;

		interrupt-parent = <&tlmm>;

		qcom,gpio-connect = <&tlmm 71 0>;

		qcom,gpio-connect = <&tlmm 90 0>;

		pinctrl-names = "default";

		pinctrl-0 = <&wcd_intr_default>;

	};



	clock_audio_up: audio_ext_clk_up {

		compatible = "qcom,audio-ref-clk";

		qcom,codec-mclk-clk-freq = <12288000>;

		qcom,audio-ref-clk-gpio = <&tlmm 62 0>;

		qcom,codec-mclk-clk-freq = <9600000>;

		pinctrl-names = "sleep", "active";

		pinctrl-0 = <&i2s_mclk_sleep>;

		pinctrl-1 = <&i2s_mclk_active>;

		#clock-cells = <1>;

	};



	wcd_rst_gpio: msm_cdc_pinctrl@77 {

	wcd_rst_gpio: msm_cdc_pinctrl@86 {

		compatible = "qcom,msm-cdc-pinctrl";

		qcom,cdc-rst-n-gpio = <&tlmm 77 0>;

		qcom,cdc-rst-n-gpio = <&tlmm 86 0>;

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_reset_active>;

		pinctrl-1 = <&cdc_reset_sleep>;
@@ -91,8 +88,8 @@ 


&i2c_3 {

	wcd934x_cdc: tavil_codec {

		compatible = "qcom,tavil-i2c-pgd";

		elemental-addr = [00 01 50 02 17 02];

		compatible = "qcom,tavil-i2c";

		reg = <0x0d>;



		interrupt-parent = <&wcd9xxx_intc>;

		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
@@ -135,7 +132,7 @@ 
		qcom,cdc-micbias3-mv = <1800>;

		qcom,cdc-micbias4-mv = <1800>;



		qcom,cdc-mclk-clk-rate = <12288000>;

		qcom,cdc-mclk-clk-rate = <9600000>;

		qcom,cdc-dmic-sample-rate = <4800000>;



		qcom,wdsp-cmpnt-dev-name = "tavil_codec";

arch/arm/boot/dts/qcom/sdxpoorwills-blsp.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -103,7 +103,6 @@ 
		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_3_active>;

		pinctrl-1 = <&i2c_3_sleep>;

		status = "disabled";

	};



	i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 76,77 */

arch/arm/boot/dts/qcom/sdxpoorwills-cdp.dts

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


#include "sdxpoorwills.dtsi"

#include "sdxpoorwills-pinctrl.dtsi"

#include "sdxpoorwills-cdp-audio-overlay.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. SDXPOORWILLS CDP";

arch/arm/boot/dts/qcom/sdxpoorwills-ion.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -20,5 +20,11 @@ 
			reg = <25>;

			qcom,ion-heap-type = "SYSTEM";

		};



		qcom,ion-heap@28 { /* AUDIO HEAP */

			reg = <28>;

			memory-region = <&audio_mem>;

			qcom,ion-heap-type = "DMA";

		};

	};

};

arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -947,12 +947,12 @@ 
		wcd9xxx_intr {

			wcd_intr_default: wcd_intr_default{

				mux {

					pins = "gpio71";

					pins = "gpio90";

					function = "gpio";

				};



				config {

					pins = "gpio71";

					pins = "gpio90";

					drive-strength = <2>; /* 2 mA */

					bias-pull-down; /* pull down */

					input-enable;
@@ -963,11 +963,11 @@ 
		cdc_reset_ctrl {

			cdc_reset_sleep: cdc_reset_sleep {

				mux {

					pins = "gpio77";

					pins = "gpio86";

					function = "gpio";

				};

				config {

					pins = "gpio77";

					pins = "gpio86";

					drive-strength = <2>;

					bias-disable;

					output-low;
@@ -976,11 +976,11 @@ 


			cdc_reset_active:cdc_reset_active {

				mux {

					pins = "gpio77";

					pins = "gpio86";

					function = "gpio";

				};

				config {

					pins = "gpio77";

					pins = "gpio86";

					drive-strength = <8>;

					bias-pull-down;

					output-high;
@@ -1063,7 +1063,7 @@ 
			pri_ws_active_master: pri_ws_active_master {

				mux {

					pins = "gpio12";

					function = "pri_mi2s_ws_a";

					function = "pri_mi2s";

				};



				config {
@@ -1077,7 +1077,7 @@ 
			pri_sck_active_master: pri_sck_active_master {

				mux {

					pins = "gpio15";

					function = "pri_mi2s_sck_a";

					function = "pri_mi2s";

				};



				config {
@@ -1091,7 +1091,7 @@ 
			pri_ws_active_slave: pri_ws_active_slave {

				mux {

					pins = "gpio12";

					function = "pri_mi2s_ws_a";

					function = "pri_mi2s";

				};



				config {
@@ -1104,7 +1104,7 @@ 
			pri_sck_active_slave: pri_sck_active_slave {

				mux {

					pins = "gpio15";

					function = "pri_mi2s_sck_a";

					function = "pri_mi2s";

				};



				config {
@@ -1117,7 +1117,7 @@ 
			pri_dout_active: pri_dout_active {

				mux {

					pins = "gpio14";

					function = "pri_mi2s_data1_a";

					function = "pri_mi2s";

				};



				config {
@@ -1147,7 +1147,7 @@ 
			pri_din_active: pri_din_active {

				mux {

					pins = "gpio13";

					function = "pri_mi2s_data0_a";

					function = "pri_mi2s";

				};



				config {