Loading drivers/crypto/msm/ice.c +14 −13 Original line number Diff line number Diff line Loading @@ -459,7 +459,7 @@ static int qcom_ice_enable(struct ice_device *ice_dev) (ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) { reg = qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BYPASS_STATUS); if ((reg & 0x80000000) != 0x0) { pr_err("%s: Bypass failed for ice = %p", pr_err("%s: Bypass failed for ice = %pK", __func__, (void *)ice_dev); WARN_ON(1); } Loading @@ -485,7 +485,7 @@ static int qcom_ice_verify_ice(struct ice_device *ice_dev) } ice_dev->ice_hw_version = rev; dev_info(ice_dev->pdev, "QC ICE %d.%d.%d device found @0x%p\n", dev_info(ice_dev->pdev, "QC ICE %d.%d.%d device found @0x%pK\n", maj_rev, min_rev, step_rev, ice_dev->mmio); Loading Loading @@ -1275,7 +1275,7 @@ static void qcom_ice_debug(struct platform_device *pdev) goto out; } pr_err("%s: =========== REGISTER DUMP (%p)===========\n", pr_err("%s: =========== REGISTER DUMP (%pK)===========\n", ice_dev->ice_instance_type, ice_dev); pr_err("%s: ICE Control: 0x%08x | ICE Reset: 0x%08x\n", Loading Loading @@ -1589,7 +1589,7 @@ struct platform_device *qcom_ice_get_pdevice(struct device_node *node) struct ice_device *ice_dev = NULL; if (!node) { pr_err("%s: invalid node %p", __func__, node); pr_err("%s: invalid node %pK", __func__, node); goto out; } Loading @@ -1606,13 +1606,14 @@ struct platform_device *qcom_ice_get_pdevice(struct device_node *node) list_for_each_entry(ice_dev, &ice_devices, list) { if (ice_dev->pdev->of_node == node) { pr_info("%s: found ice device %p\n", __func__, ice_dev); pr_info("%s: found ice device %pK\n", __func__, ice_dev); break; } } ice_pdev = to_platform_device(ice_dev->pdev); pr_info("%s: matching platform device %p\n", __func__, ice_pdev); pr_info("%s: matching platform device %pK\n", __func__, ice_pdev); out: return ice_pdev; } Loading Loading @@ -1650,7 +1651,7 @@ static int enable_ice_setup(struct ice_device *ice_dev) } ret = regulator_enable(ice_dev->reg); if (ret) { pr_err("%s:%p: Could not enable regulator\n", pr_err("%s:%pK: Could not enable regulator\n", __func__, ice_dev); goto out; } Loading @@ -1658,7 +1659,7 @@ static int enable_ice_setup(struct ice_device *ice_dev) /* Setup Clocks */ if (qcom_ice_enable_clocks(ice_dev, true)) { pr_err("%s:%p:%s Could not enable clocks\n", __func__, pr_err("%s:%pK:%s Could not enable clocks\n", __func__, ice_dev, ice_dev->ice_instance_type); goto out_reg; } Loading @@ -1670,7 +1671,7 @@ static int enable_ice_setup(struct ice_device *ice_dev) ret = qcom_ice_set_bus_vote(ice_dev, vote); if (ret) { pr_err("%s:%p: failed %d\n", __func__, ice_dev, ret); pr_err("%s:%pK: failed %d\n", __func__, ice_dev, ret); goto out_clocks; } Loading Loading @@ -1702,19 +1703,19 @@ static int disable_ice_setup(struct ice_device *ice_dev) /* Setup Bus Vote */ vote = qcom_ice_get_bus_vote(ice_dev, "MIN"); if (vote < 0) { pr_err("%s:%p: Unable to get bus vote\n", __func__, ice_dev); pr_err("%s:%pK: Unable to get bus vote\n", __func__, ice_dev); goto out_disable_clocks; } ret = qcom_ice_set_bus_vote(ice_dev, vote); if (ret) pr_err("%s:%p: failed %d\n", __func__, ice_dev, ret); pr_err("%s:%pK: failed %d\n", __func__, ice_dev, ret); out_disable_clocks: /* Setup Clocks */ if (qcom_ice_enable_clocks(ice_dev, false)) pr_err("%s:%p:%s Could not disable clocks\n", __func__, pr_err("%s:%pK:%s Could not disable clocks\n", __func__, ice_dev, ice_dev->ice_instance_type); /* Setup Regulator */ Loading @@ -1725,7 +1726,7 @@ static int disable_ice_setup(struct ice_device *ice_dev) } ret = regulator_disable(ice_dev->reg); if (ret) { pr_err("%s:%p: Could not disable regulator\n", pr_err("%s:%pK: Could not disable regulator\n", __func__, ice_dev); goto out; } Loading drivers/crypto/msm/ota_crypto.c +2 −2 Original line number Diff line number Diff line Loading @@ -172,7 +172,7 @@ static int qcota_release(struct inode *inode, struct file *file) podev = file->private_data; if (podev != NULL && podev->magic != OTA_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); } Loading Loading @@ -440,7 +440,7 @@ static long qcota_ioctl(struct file *file, podev = file->private_data; if (podev == NULL || podev->magic != OTA_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); return -ENOENT; } Loading drivers/crypto/msm/qce50.c +4 −4 Original line number Diff line number Diff line Loading @@ -1164,7 +1164,7 @@ static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev, int req_info) #define QCE_WRITE_REG(val, addr) \ { \ pr_info(" [0x%p] 0x%x\n", addr, (uint32_t)val); \ pr_info(" [0x%pK] 0x%x\n", addr, (uint32_t)val); \ writel_relaxed(val, addr); \ } Loading Loading @@ -2739,7 +2739,7 @@ static int qce_sps_init_ep_conn(struct qce_device *pce_dev, sps_event->callback = NULL; } pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%p\n", pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%pK\n", is_producer ? "PRODUCER(RX/OUT)" : "CONSUMER(TX/IN)", (uintptr_t)sps_pipe_info, &sps_connect_info->desc.phys_base); goto out; Loading Loading @@ -2901,7 +2901,7 @@ static int qce_sps_get_bam(struct qce_device *pce_dev) bam.ipc_loglevel = QCE_BAM_DEFAULT_IPC_LOGLVL; bam.options |= SPS_BAM_CACHED_WP; pr_debug("bam physical base=0x%lx\n", (uintptr_t)bam.phys_addr); pr_debug("bam virtual base=0x%p\n", bam.virt_addr); pr_debug("bam virtual base=0x%pK\n", bam.virt_addr); /* Register CE Peripheral BAM device to SPS driver */ rc = sps_register_bam_device(&bam, &pbam->handle); Loading Loading @@ -3005,7 +3005,7 @@ static void print_notify_debug(struct sps_event_notify *notify) phys_addr_t addr = DESC_FULL_ADDR((phys_addr_t) notify->data.transfer.iovec.flags, notify->data.transfer.iovec.addr); pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%p\n", pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%pK\n", notify->event_id, &addr, notify->data.transfer.iovec.size, notify->data.transfer.iovec.flags, Loading drivers/crypto/msm/qcedev.c +2 −2 Original line number Diff line number Diff line Loading @@ -269,7 +269,7 @@ static int qcedev_release(struct inode *inode, struct file *file) handle = file->private_data; podev = handle->cntl; if (podev != NULL && podev->magic != QCEDEV_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); } kzfree(handle); Loading Loading @@ -1657,7 +1657,7 @@ static inline long qcedev_ioctl(struct file *file, podev = handle->cntl; qcedev_areq.handle = handle; if (podev == NULL || podev->magic != QCEDEV_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); return -ENOENT; } Loading drivers/crypto/msm/qcrypto.c +11 −11 Original line number Diff line number Diff line Loading @@ -265,7 +265,7 @@ static void qcrypto_free_req_control(struct crypto_engine *pce, preq->arsp = NULL; /* free req */ if (xchg(&preq->in_use, false) == false) pr_warn("request info %p free already\n", preq); pr_warn("request info %pK free already\n", preq); else atomic_dec(&pce->req_count); } Loading Loading @@ -1759,7 +1759,7 @@ static void _qce_ahash_complete(void *cookie, unsigned char *digest, } #ifdef QCRYPTO_DEBUG dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %p ret %d\n", dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %pK ret %d\n", areq, ret); #endif if (digest) { Loading Loading @@ -1818,7 +1818,7 @@ static void _qce_ablk_cipher_complete(void *cookie, unsigned char *icb, } #ifdef QCRYPTO_DEBUG dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %p ret %d\n", dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %pK ret %d\n", areq, ret); #endif if (iv) Loading Loading @@ -2520,7 +2520,7 @@ static int _qcrypto_enc_aes_ecb(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2550,7 +2550,7 @@ static int _qcrypto_enc_aes_cbc(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2580,7 +2580,7 @@ static int _qcrypto_enc_aes_ctr(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2768,7 +2768,7 @@ static int _qcrypto_dec_aes_ecb(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2798,7 +2798,7 @@ static int _qcrypto_dec_aes_cbc(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2828,7 +2828,7 @@ static int _qcrypto_dec_aes_ctr(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -3394,7 +3394,7 @@ static int _qcrypto_aead_encrypt_aes_cbc(struct aead_request *req) #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_aead_encrypt_aes_cbc: %p\n", req); "_qcrypto_aead_encrypt_aes_cbc: %pK\n", req); #endif rctx = aead_request_ctx(req); Loading Loading @@ -3425,7 +3425,7 @@ static int _qcrypto_aead_decrypt_aes_cbc(struct aead_request *req) #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_aead_decrypt_aes_cbc: %p\n", req); "_qcrypto_aead_decrypt_aes_cbc: %pK\n", req); #endif rctx = aead_request_ctx(req); rctx->aead = 1; Loading Loading
drivers/crypto/msm/ice.c +14 −13 Original line number Diff line number Diff line Loading @@ -459,7 +459,7 @@ static int qcom_ice_enable(struct ice_device *ice_dev) (ICE_REV(ice_dev->ice_hw_version, MINOR) >= 1))) { reg = qcom_ice_readl(ice_dev, QCOM_ICE_REGS_BYPASS_STATUS); if ((reg & 0x80000000) != 0x0) { pr_err("%s: Bypass failed for ice = %p", pr_err("%s: Bypass failed for ice = %pK", __func__, (void *)ice_dev); WARN_ON(1); } Loading @@ -485,7 +485,7 @@ static int qcom_ice_verify_ice(struct ice_device *ice_dev) } ice_dev->ice_hw_version = rev; dev_info(ice_dev->pdev, "QC ICE %d.%d.%d device found @0x%p\n", dev_info(ice_dev->pdev, "QC ICE %d.%d.%d device found @0x%pK\n", maj_rev, min_rev, step_rev, ice_dev->mmio); Loading Loading @@ -1275,7 +1275,7 @@ static void qcom_ice_debug(struct platform_device *pdev) goto out; } pr_err("%s: =========== REGISTER DUMP (%p)===========\n", pr_err("%s: =========== REGISTER DUMP (%pK)===========\n", ice_dev->ice_instance_type, ice_dev); pr_err("%s: ICE Control: 0x%08x | ICE Reset: 0x%08x\n", Loading Loading @@ -1589,7 +1589,7 @@ struct platform_device *qcom_ice_get_pdevice(struct device_node *node) struct ice_device *ice_dev = NULL; if (!node) { pr_err("%s: invalid node %p", __func__, node); pr_err("%s: invalid node %pK", __func__, node); goto out; } Loading @@ -1606,13 +1606,14 @@ struct platform_device *qcom_ice_get_pdevice(struct device_node *node) list_for_each_entry(ice_dev, &ice_devices, list) { if (ice_dev->pdev->of_node == node) { pr_info("%s: found ice device %p\n", __func__, ice_dev); pr_info("%s: found ice device %pK\n", __func__, ice_dev); break; } } ice_pdev = to_platform_device(ice_dev->pdev); pr_info("%s: matching platform device %p\n", __func__, ice_pdev); pr_info("%s: matching platform device %pK\n", __func__, ice_pdev); out: return ice_pdev; } Loading Loading @@ -1650,7 +1651,7 @@ static int enable_ice_setup(struct ice_device *ice_dev) } ret = regulator_enable(ice_dev->reg); if (ret) { pr_err("%s:%p: Could not enable regulator\n", pr_err("%s:%pK: Could not enable regulator\n", __func__, ice_dev); goto out; } Loading @@ -1658,7 +1659,7 @@ static int enable_ice_setup(struct ice_device *ice_dev) /* Setup Clocks */ if (qcom_ice_enable_clocks(ice_dev, true)) { pr_err("%s:%p:%s Could not enable clocks\n", __func__, pr_err("%s:%pK:%s Could not enable clocks\n", __func__, ice_dev, ice_dev->ice_instance_type); goto out_reg; } Loading @@ -1670,7 +1671,7 @@ static int enable_ice_setup(struct ice_device *ice_dev) ret = qcom_ice_set_bus_vote(ice_dev, vote); if (ret) { pr_err("%s:%p: failed %d\n", __func__, ice_dev, ret); pr_err("%s:%pK: failed %d\n", __func__, ice_dev, ret); goto out_clocks; } Loading Loading @@ -1702,19 +1703,19 @@ static int disable_ice_setup(struct ice_device *ice_dev) /* Setup Bus Vote */ vote = qcom_ice_get_bus_vote(ice_dev, "MIN"); if (vote < 0) { pr_err("%s:%p: Unable to get bus vote\n", __func__, ice_dev); pr_err("%s:%pK: Unable to get bus vote\n", __func__, ice_dev); goto out_disable_clocks; } ret = qcom_ice_set_bus_vote(ice_dev, vote); if (ret) pr_err("%s:%p: failed %d\n", __func__, ice_dev, ret); pr_err("%s:%pK: failed %d\n", __func__, ice_dev, ret); out_disable_clocks: /* Setup Clocks */ if (qcom_ice_enable_clocks(ice_dev, false)) pr_err("%s:%p:%s Could not disable clocks\n", __func__, pr_err("%s:%pK:%s Could not disable clocks\n", __func__, ice_dev, ice_dev->ice_instance_type); /* Setup Regulator */ Loading @@ -1725,7 +1726,7 @@ static int disable_ice_setup(struct ice_device *ice_dev) } ret = regulator_disable(ice_dev->reg); if (ret) { pr_err("%s:%p: Could not disable regulator\n", pr_err("%s:%pK: Could not disable regulator\n", __func__, ice_dev); goto out; } Loading
drivers/crypto/msm/ota_crypto.c +2 −2 Original line number Diff line number Diff line Loading @@ -172,7 +172,7 @@ static int qcota_release(struct inode *inode, struct file *file) podev = file->private_data; if (podev != NULL && podev->magic != OTA_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); } Loading Loading @@ -440,7 +440,7 @@ static long qcota_ioctl(struct file *file, podev = file->private_data; if (podev == NULL || podev->magic != OTA_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); return -ENOENT; } Loading
drivers/crypto/msm/qce50.c +4 −4 Original line number Diff line number Diff line Loading @@ -1164,7 +1164,7 @@ static void _qce_dump_descr_fifos_dbg(struct qce_device *pce_dev, int req_info) #define QCE_WRITE_REG(val, addr) \ { \ pr_info(" [0x%p] 0x%x\n", addr, (uint32_t)val); \ pr_info(" [0x%pK] 0x%x\n", addr, (uint32_t)val); \ writel_relaxed(val, addr); \ } Loading Loading @@ -2739,7 +2739,7 @@ static int qce_sps_init_ep_conn(struct qce_device *pce_dev, sps_event->callback = NULL; } pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%p\n", pr_debug("success, %s : pipe_handle=0x%lx, desc fifo base (phy) = 0x%pK\n", is_producer ? "PRODUCER(RX/OUT)" : "CONSUMER(TX/IN)", (uintptr_t)sps_pipe_info, &sps_connect_info->desc.phys_base); goto out; Loading Loading @@ -2901,7 +2901,7 @@ static int qce_sps_get_bam(struct qce_device *pce_dev) bam.ipc_loglevel = QCE_BAM_DEFAULT_IPC_LOGLVL; bam.options |= SPS_BAM_CACHED_WP; pr_debug("bam physical base=0x%lx\n", (uintptr_t)bam.phys_addr); pr_debug("bam virtual base=0x%p\n", bam.virt_addr); pr_debug("bam virtual base=0x%pK\n", bam.virt_addr); /* Register CE Peripheral BAM device to SPS driver */ rc = sps_register_bam_device(&bam, &pbam->handle); Loading Loading @@ -3005,7 +3005,7 @@ static void print_notify_debug(struct sps_event_notify *notify) phys_addr_t addr = DESC_FULL_ADDR((phys_addr_t) notify->data.transfer.iovec.flags, notify->data.transfer.iovec.addr); pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%p\n", pr_debug("sps ev_id=%d, addr=0x%pa, size=0x%x, flags=0x%x user=0x%pK\n", notify->event_id, &addr, notify->data.transfer.iovec.size, notify->data.transfer.iovec.flags, Loading
drivers/crypto/msm/qcedev.c +2 −2 Original line number Diff line number Diff line Loading @@ -269,7 +269,7 @@ static int qcedev_release(struct inode *inode, struct file *file) handle = file->private_data; podev = handle->cntl; if (podev != NULL && podev->magic != QCEDEV_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); } kzfree(handle); Loading Loading @@ -1657,7 +1657,7 @@ static inline long qcedev_ioctl(struct file *file, podev = handle->cntl; qcedev_areq.handle = handle; if (podev == NULL || podev->magic != QCEDEV_MAGIC) { pr_err("%s: invalid handle %p\n", pr_err("%s: invalid handle %pK\n", __func__, podev); return -ENOENT; } Loading
drivers/crypto/msm/qcrypto.c +11 −11 Original line number Diff line number Diff line Loading @@ -265,7 +265,7 @@ static void qcrypto_free_req_control(struct crypto_engine *pce, preq->arsp = NULL; /* free req */ if (xchg(&preq->in_use, false) == false) pr_warn("request info %p free already\n", preq); pr_warn("request info %pK free already\n", preq); else atomic_dec(&pce->req_count); } Loading Loading @@ -1759,7 +1759,7 @@ static void _qce_ahash_complete(void *cookie, unsigned char *digest, } #ifdef QCRYPTO_DEBUG dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %p ret %d\n", dev_info(&pengine->pdev->dev, "_qce_ahash_complete: %pK ret %d\n", areq, ret); #endif if (digest) { Loading Loading @@ -1818,7 +1818,7 @@ static void _qce_ablk_cipher_complete(void *cookie, unsigned char *icb, } #ifdef QCRYPTO_DEBUG dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %p ret %d\n", dev_info(&pengine->pdev->dev, "_qce_ablk_cipher_complete: %pK ret %d\n", areq, ret); #endif if (iv) Loading Loading @@ -2520,7 +2520,7 @@ static int _qcrypto_enc_aes_ecb(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ecb: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2550,7 +2550,7 @@ static int _qcrypto_enc_aes_cbc(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_cbc: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2580,7 +2580,7 @@ static int _qcrypto_enc_aes_ctr(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_enc_aes_ctr: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2768,7 +2768,7 @@ static int _qcrypto_dec_aes_ecb(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ecb: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2798,7 +2798,7 @@ static int _qcrypto_dec_aes_cbc(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_cbc: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -2828,7 +2828,7 @@ static int _qcrypto_dec_aes_ctr(struct ablkcipher_request *req) WARN_ON(crypto_tfm_alg_type(req->base.tfm) != CRYPTO_ALG_TYPE_ABLKCIPHER); #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %p\n", req); dev_info(&ctx->pengine->pdev->dev, "_qcrypto_dec_aes_ctr: %pK\n", req); #endif if ((ctx->enc_key_len == AES_KEYSIZE_192) && Loading Loading @@ -3394,7 +3394,7 @@ static int _qcrypto_aead_encrypt_aes_cbc(struct aead_request *req) #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_aead_encrypt_aes_cbc: %p\n", req); "_qcrypto_aead_encrypt_aes_cbc: %pK\n", req); #endif rctx = aead_request_ctx(req); Loading Loading @@ -3425,7 +3425,7 @@ static int _qcrypto_aead_decrypt_aes_cbc(struct aead_request *req) #ifdef QCRYPTO_DEBUG dev_info(&ctx->pengine->pdev->dev, "_qcrypto_aead_decrypt_aes_cbc: %p\n", req); "_qcrypto_aead_decrypt_aes_cbc: %pK\n", req); #endif rctx = aead_request_ctx(req); rctx->aead = 1; Loading