Loading arch/arm64/boot/dts/qcom/sdm845-sde.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -194,6 +194,7 @@ qcom,sde-dspp-igc = <0x0 0x00030001>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; qcom,sde-dspp-gamut = <0x1000 0x00040000>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; }; Loading drivers/gpu/drm/msm/sde/sde_color_processing.c +1 −0 Original line number Diff line number Diff line Loading @@ -1064,6 +1064,7 @@ static void dspp_pcc_install_property(struct drm_crtc *crtc) "SDE_DSPP_PCC_V", version); switch (version) { case 1: case 4: sde_cp_crtc_install_blob_property(crtc, feature_name, SDE_CP_CRTC_DSPP_PCC, sizeof(struct drm_msm_pcc)); break; Loading drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h +6 −0 Original line number Diff line number Diff line Loading @@ -50,4 +50,10 @@ enum { #define IGC_DIS 0 #define IGC_DITHER_DATA_MASK (BIT(4) - 1) #define PCC_NUM_PLANES 3 #define PCC_NUM_COEFF 11 #define PCC_EN BIT(0) #define PCC_DIS 0 #define PCC_C_OFF 0x4 #endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */ drivers/gpu/drm/msm/sde/sde_hw_dspp.c +9 −0 Original line number Diff line number Diff line Loading @@ -58,6 +58,15 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7; else if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x4, 0x0))) { ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4; else c->ops.setup_pcc = NULL; } break; case SDE_DSPP_HSIC: if (c->cap->sblk->hsic.version == Loading drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1.c +1 −0 Original line number Diff line number Diff line Loading @@ -91,6 +91,7 @@ static u32 v1_supported[REG_DMA_FEATURES_MAX] = { [VLUT] = GRP_DSPP_HW_BLK_SELECT, [GC] = GRP_DSPP_HW_BLK_SELECT, [IGC] = DSPP_IGC | GRP_DSPP_HW_BLK_SELECT, [PCC] = GRP_DSPP_HW_BLK_SELECT, }; static int validate_dma_cfg(struct sde_reg_dma_setup_ops_cfg *cfg); Loading Loading
arch/arm64/boot/dts/qcom/sdm845-sde.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -194,6 +194,7 @@ qcom,sde-dspp-igc = <0x0 0x00030001>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; qcom,sde-dspp-gamut = <0x1000 0x00040000>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; }; Loading
drivers/gpu/drm/msm/sde/sde_color_processing.c +1 −0 Original line number Diff line number Diff line Loading @@ -1064,6 +1064,7 @@ static void dspp_pcc_install_property(struct drm_crtc *crtc) "SDE_DSPP_PCC_V", version); switch (version) { case 1: case 4: sde_cp_crtc_install_blob_property(crtc, feature_name, SDE_CP_CRTC_DSPP_PCC, sizeof(struct drm_msm_pcc)); break; Loading
drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h +6 −0 Original line number Diff line number Diff line Loading @@ -50,4 +50,10 @@ enum { #define IGC_DIS 0 #define IGC_DITHER_DATA_MASK (BIT(4) - 1) #define PCC_NUM_PLANES 3 #define PCC_NUM_COEFF 11 #define PCC_EN BIT(0) #define PCC_DIS 0 #define PCC_C_OFF 0x4 #endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */
drivers/gpu/drm/msm/sde/sde_hw_dspp.c +9 −0 Original line number Diff line number Diff line Loading @@ -58,6 +58,15 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7; else if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x4, 0x0))) { ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4; else c->ops.setup_pcc = NULL; } break; case SDE_DSPP_HSIC: if (c->cap->sblk->hsic.version == Loading
drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1.c +1 −0 Original line number Diff line number Diff line Loading @@ -91,6 +91,7 @@ static u32 v1_supported[REG_DMA_FEATURES_MAX] = { [VLUT] = GRP_DSPP_HW_BLK_SELECT, [GC] = GRP_DSPP_HW_BLK_SELECT, [IGC] = DSPP_IGC | GRP_DSPP_HW_BLK_SELECT, [PCC] = GRP_DSPP_HW_BLK_SELECT, }; static int validate_dma_cfg(struct sde_reg_dma_setup_ops_cfg *cfg); Loading