msm: kgsl: initial implementation of A6XX GMU driver

Qualcomm Technologies, Inc. GPU Graphics Management Unit (GMU)

Required properties:

- compatible :

	- "qcom,gpu-gmu"

- reg:		Specifies the PDC register base address and size.

- reg-names:		Resource names used for the physical address

		and length of PDC registers.

- interrupts:	Interrupt mapping for GMU and HFI IRQs.

- interrupt-names:	String property to describe the name of each interrupt.

Bus Scaling Data:

qcom,msm-bus,name: String property to describe the name of bus client.

qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.

qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.

qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:

		<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1

		<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2

		<..  ..  .. ..>, <..  ..  .. ..>; // For Bus Scaling Usecase n

		This property is a series of all vectors for all Bus Scaling Usecases.

		Each set of vectors for each usecase describes bandwidth votes for a combination

		of src/dst ports.  The driver will set the desired use case based on the selected

		power level and the desired bandwidth vote will be registered for the port pairs.

GMU GDSC/regulators:

- regulator-names:	List of regulator name strings

- vddcx-supply:		Phandle for vddcx regulator device node.

- vdd-supply:		Phandle for vdd regulator device node.

- clock:	List of clocks to be used for GMU register access and DCVS. See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for information about the format. For each clock specified

		  here, there must be a corresponding entry in clock-names

		  (see below).

- clock-names:	List of clock names corresponding to the clocks specified in

		  the "clocks" property (above). See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for more info. Currently GMU required these clock names:

			"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",

			"rbcpr_clk"

- qcom,gmu-pwrlevels: device node defines a set of GMU power levels. It has

		following required properties:

		- compatible : "qcom,gmu-pwrlevels"

		- qcom,gmu-pwrlevel: a single power level. Each power level has

		  below properties:

			- reg: index of the powerlevel (0 = highest perf)

			- qcom, gmu-freq: GMU frequency for the power level in Hz.

- List of sub nodes, one for each of the translation context banks needed

		for GMU to access system memory in different operating mode. Currently

		supported names are:

		- gmu_user: used for GMU 'user' mode address space.

		- gmu_kernel: used for GMU 'kernel' mode address space.

		Each sub node has the following required properties:

		- compatible : "qcom,smmu-gmu-user-cb" or "qcom,smmu-gmu-kernel-cb"

		- iommus : Specifies the SID's used by this context bank, this

			needs to be <kgsl_smmu SID> pair, kgsl_smmu is the string

			parsed by iommu driver to match this context bank with the

			kgsl_smmu device defined in iommu device tree. On targets

			where the msm iommu driver is used rather than the arm smmu

			driver, this property may be absent.

Example:

gmu: qcom,gmu {

	label = "kgsl-gmu";

	compatible = "qcom,gpu-gmu";

	reg = <0xb200000 0x300000>;

	reg-names = "kgsl_gmu_pdc_reg";

	interrupts = <0 301 0>, <0 302 0>;

	interrupt-names = "kgsl_gmu_irq", "kgsl_hfi_irq";

	qcom,msm-bus,name = "cnoc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<26 10036 0 0>,		// CNOC off

			<26 10036 0 100>;	// CNOC on

	regulator-name = "vddcx", "vdd";

	vddcx-supply = <&gpu_cx_gdsc>;

	vdd-supply = <&gpu_gx_gdsc>;

	clocks = <&clock_gpugcc clk_gcc_gmu_clk>,

		<&clock_gcc GCC_GPU_CFG_AHB_CLK>,

		<&clock_gpucc GPU_CC_CXO_CLK>,

		<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

		<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

		<&clock_gpucc GPU_CC_RBCPR_CLK>;

	clock-names = "gmu_clk", "ahb_clk", "cxo_clk",

				"axi_clk", "memnoc_clk", "rbcpr_clk";

	qcom,gmu-pwrlevels {

	      compatible = "qcom,gmu-pwrlevels";

	      qcom,gpu-pwrlevel@0 {

	          reg = <0>;

	          qcom,gmu-freq = <500000000>;

	      };

	      qcom,gpu-pwrlevel@1 {

	          reg = <1>;

	          qcom,gmu-freq = <200000000>;

	      };

	      qcom,gpu-pwrlevel@2 {

	          reg = <2>;

	          qcom,gmu-freq = <0>;

	      };

	};

	gmu_user: gmu_user {

	      compatible = "qcom,smmu-gmu-user-cb";

	      iommus = <&kgsl_smmu 4>;

	};

	gmu_kernel: gmu_kernel {

	      compatible = "qcom,smmu-gmu-kernel-cb";

	      iommus = <&kgsl_smmu 5>;

	};

};

- qcom,gpu-quirk-lmloadkill-disable:

				Use register setting to disable local memory(LM) feature

				to avoid corner case error

- qcom,gpu-quirk-hfi-use-reg:

				Use registers to replace DCVS HFI message to avoid GMU failure

				to access system memory during IFPC

KGSL Memory Pools:

- qcom,gpu-mempools:		Container for sets of GPU mempools.Multiple sets

	kgsl_mmu.o \

	kgsl_snapshot.o \

	kgsl_events.o \

	kgsl_pool.o

	kgsl_pool.o \

	kgsl_gmu.o \

	kgsl_hfi.o

msm_kgsl_core-$(CONFIG_QCOM_KGSL_IOMMU) += kgsl_iommu.o

msm_kgsl_core-$(CONFIG_DEBUG_FS) += kgsl_debugfs.o

#define A6XX_VBIF_XIN_HALT_CTRL0                0x3080

#define A6XX_VBIF_XIN_HALT_CTRL1                0x3081

/* GMU registers */

#define A6XX_GMU_CX_ALWAYS_ON_COUNTER_L         0x1f888

#define A6XX_GMU_CX_ALWAYS_ON_COUNTER_H         0x1f889

/* GMU control registers */

#define A6XX_GMU_GX_SPTPRAC_POWER_CONTROL	0x1A881

#define A6XX_GMU_CM3_ITCM_START			0x1B400

#define A6XX_GMU_CM3_DTCM_START			0x1C400

#define A6XX_GMU_BOOT_SLUMBER_OPTION		0x1CBF8

#define A6XX_GMU_GX_VOTE_IDX			0x1CBF9

#define A6XX_GMU_MX_VOTE_IDX			0x1CBFA

#define A6XX_GMU_DCVS_ACK_OPTION		0x1CBFC

#define A6XX_GMU_DCVS_PERF_SETTING		0x1CBFD

#define A6XX_GMU_DCVS_BW_SETTING		0x1CBFE

#define A6XX_GMU_DCVS_RETURN			0x1CBFF

#define A6XX_GMU_CM3_SYSRESET			0x1F800

#define A6XX_GMU_CM3_BOOT_CONFIG		0x1F801

#define A6XX_GMU_CM3_FW_INIT_RESULT		0x1F81C

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2

#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS		0x1F8D0

#define A6XX_GMU_GPU_NAP_CTRL			0x1F8E4

#define A6XX_GMU_RPMH_CTRL			0x1F8E8

#define A6XX_GMU_RPMH_HYST_CTRL			0x1F8E9

#define A6XX_GMU_RPMH_POWER_STATE		0x1F8EC

/* HFI registers*/

#define A6XX_GMU_ALWAYS_ON_COUNTER_L		0x1F888

#define A6XX_GMU_ALWAYS_ON_COUNTER_H		0x1F889

#define A6XX_GMU_GMU_PWR_COL_KEEPALIVE		0x1F8C3

#define A6XX_GMU_HFI_CTRL_STATUS		0x1F980

#define A6XX_GMU_HFI_VERSION_INFO		0x1F981

#define A6XX_GMU_HFI_SFR_ADDR			0x1F982

#define A6XX_GMU_HFI_MMAP_ADDR			0x1F983

#define A6XX_GMU_HFI_QTBL_INFO			0x1F984

#define A6XX_GMU_HFI_QTBL_ADDR			0x1F985

#define A6XX_GMU_HFI_CTRL_INIT			0x1F986

#define A6XX_GMU_GMU2HOST_INTR_SET		0x1F990

#define A6XX_GMU_GMU2HOST_INTR_CLR		0x1F991

#define A6XX_GMU_GMU2HOST_INTR_INFO		0x1F992

#define A6XX_GMU_GMU2HOST_INTR_MASK		0x1F993

#define A6XX_GMU_HOST2GMU_INTR_SET		0x1F994

#define A6XX_GMU_HOST2GMU_INTR_CLR		0x1F995

#define A6XX_GMU_HOST2GMU_INTR_RAW_INFO		0x1F996

#define A6XX_GMU_HOST2GMU_INTR_EN_0		0x1F997

#define A6XX_GMU_HOST2GMU_INTR_EN_1		0x1F998

#define A6XX_GMU_HOST2GMU_INTR_EN_2		0x1F999

#define A6XX_GMU_HOST2GMU_INTR_EN_3		0x1F99A

#define A6XX_GMU_HOST2GMU_INTR_INFO_0		0x1F99B

#define A6XX_GMU_HOST2GMU_INTR_INFO_1		0x1F99C

#define A6XX_GMU_HOST2GMU_INTR_INFO_2		0x1F99D

#define A6XX_GMU_HOST2GMU_INTR_INFO_3		0x1F99E

#define A6XX_GMU_GENERAL_7			0x1F9CC

#define A6XX_GMU_AO_INTERRUPT_EN		0x23B03

#define A6XX_GMU_HOST_INTERRUPT_CLR		0x23B04

#define A6XX_GMU_HOST_INTERRUPT_STATUS		0x23B05

#define A6XX_GMU_HOST_INTERRUPT_MASK		0x23B06

#define A6XX_GMU_GPU_CX_BUSY_STATUS		0x23B0C

#define A6XX_GMU_AHB_FENCE_STATUS		0x23B13

#define A6XX_GMU_RBBM_INT_UNMASKED_STATUS	0x23B15

#define A6XX_GMU_AO_SPARE_CNTL			0x23B16

/* GMU RSC control registers */

#define A6XX_GMU_RSCC_CONTROL_REQ		0x23B07

#define A6XX_GMU_RSCC_CONTROL_ACK		0x23B08

/* FENCE control registers */

#define A6XX_GMU_AHB_FENCE_RANGE_0		0x23B11

#define A6XX_GMU_AHB_FENCE_RANGE_1		0x23B12

/* GPU RSC sequencer registers */

#define	A6XX_RSCC_PDC_SEQ_START_ADDR			0x23408

#define A6XX_RSCC_PDC_MATCH_VALUE_LO			0x23409

#define A6XX_RSCC_PDC_MATCH_VALUE_HI			0x2340A

#define A6XX_RSCC_PDC_SLAVE_ID_DRV0			0x2340B

#define A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR			0x2340D

#define A6XX_RSCC_HIDDEN_TCS_CMD0_DATA			0x2340E

#define A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0	0x23482

#define A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0	0x23483

#define A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0		0x23489

#define A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0		0x2348C

#define A6XX_RSCC_OVERRIDE_START_ADDR			0x23500

#define A6XX_RSCC_SEQ_BUSY_DRV0				0x23501

#define A6XX_RSCC_SEQ_MEM_0_DRV0			0x23580

/* GPU PDC sequencer registers in AOSS.RPMh domain */

#define	PDC_GPU_ENABLE_PDC			0x21140

#define PDC_GPU_SEQ_START_ADDR			0x21148

#define PDC_GPU_TCS0_CONTROL			0x21540

#define PDC_GPU_TCS0_CMD_ENABLE_BANK		0x21541

#define PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK	0x21542

#define PDC_GPU_TCS0_CMD0_MSGID			0x21543

#define PDC_GPU_TCS0_CMD0_ADDR			0x21544

#define PDC_GPU_TCS0_CMD0_DATA			0x21545

#define PDC_GPU_TCS1_CONTROL			0x21572

#define PDC_GPU_TCS1_CMD_ENABLE_BANK		0x21573

#define PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK	0x21574

#define PDC_GPU_TCS1_CMD0_MSGID			0x21575

#define PDC_GPU_TCS1_CMD0_ADDR			0x21576

#define PDC_GPU_TCS1_CMD0_DATA			0x21577

#define PDC_GPU_TIMESTAMP_UNIT1_EN_DRV0		0x23489

#define PDC_GPU_SEQ_MEM_0			0xA0000

#endif /* _A6XX_REG_H */

		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_64BIT,

		.features = ADRENO_64BIT |

			ADRENO_GPMU | ADRENO_RPMH,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a630_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a540_gpmu.fw2",

		.gpmu_major = 0x0,

		.gpmu_minor = 0x005,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

	},

};