Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b0f20ff9 authored by Santosh Shilimkar's avatar Santosh Shilimkar Committed by Tony Lindgren
Browse files

omap4: l2x0: Set share override bit 



Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption

Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 11e02640

arch/arm/mach-omap2/omap4-common.c

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ static int __init omap_l2_cache_init(void) 
		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;

	} else {

		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |

			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |

			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |

			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT));

	}