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Commit b0823d0f authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: clk-alpha-pll: Check for the parent rate during round_rate 



The parent rate passed in to the round_rate operation of the
alpha PLL could be 0. Account for this and fix the UBSAN warning:

UBSAN: Undefined behaviour in drivers/clk/qcom/clk-alpha-pll.c:311:137
division by zero

Change-Id: Ie6834a4e52589251fa7b7287ee292aafc92342a1
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 925b2207

drivers/clk/qcom/clk-alpha-pll.c

+9 −0
Original line number Diff line number Diff line
@@ -307,6 +307,15 @@ alpha_pll_round_rate(const struct clk_alpha_pll *pll, unsigned long rate, 
	u64 quotient;

	int alpha_bw = ALPHA_BITWIDTH;



	/*

	 * The PLLs parent rate is zero probably since the parent hasn't

	 * registered yet. Return early with the requested rate.

	 */

	if (!prate) {

		pr_debug("PLLs parent rate hasn't been initialized.\n");

		return rate;

	}



	quotient = rate;

	remainder = do_div(quotient, prate);

	*l = quotient;