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Commit b039dd4b authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: gcc-sdm845: Remove control of some CLKREF_EN registers" into msm-4.9

parents ad3eda81 dbf26f91

drivers/clk/qcom/gcc-sdm845.c

+0 −42
Original line number Diff line number Diff line
@@ -1468,19 +1468,6 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = { 
	},

};



static struct clk_branch gcc_cxo_tx1_clkref_clk = {

	.halt_reg = 0x8c020,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c020,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cxo_tx1_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_ddrss_gpu_axi_clk = {

	.halt_reg = 0x44038,

	.halt_check = BRANCH_VOTED,
@@ -2433,32 +2420,6 @@ static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 
	},

};



static struct clk_branch gcc_rx1_usb2_clkref_clk = {

	.halt_reg = 0x8c014,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c014,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_rx1_usb2_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_rx2_qlink_clkref_clk = {

	.halt_reg = 0x8c018,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_rx2_qlink_clkref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdcc2_ahb_clk = {

	.halt_reg = 0x14008,

	.halt_check = BRANCH_HALT,
@@ -3151,7 +3112,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,

	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,

	[GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,

	[GCC_CXO_TX1_CLKREF_CLK] = &gcc_cxo_tx1_clkref_clk.clkr,

	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,

	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,

	[GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
@@ -3238,8 +3198,6 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,

	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,

	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,

	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,

	[GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr,

	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,

	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,

	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,

include/dt-bindings/clock/qcom,gcc-sdm845.h

+152 −155
Original line number Diff line number Diff line
@@ -35,161 +35,158 @@ 
#define GCC_CPUSS_GNOC_CLK					17

#define GCC_CPUSS_RBCPR_CLK					18

#define GCC_CPUSS_RBCPR_CLK_SRC					19

#define GCC_CXO_TX1_CLKREF_CLK					20

#define GCC_DDRSS_GPU_AXI_CLK					21

#define GCC_DISP_AHB_CLK					22

#define GCC_DISP_AXI_CLK					23

#define GCC_DISP_GPLL0_CLK_SRC					24

#define GCC_DISP_GPLL0_DIV_CLK_SRC				25

#define GCC_DISP_XO_CLK						26

#define GCC_GP1_CLK						27

#define GCC_GP1_CLK_SRC						28

#define GCC_GP2_CLK						29

#define GCC_GP2_CLK_SRC						30

#define GCC_GP3_CLK						31

#define GCC_GP3_CLK_SRC						32

#define GCC_GPU_CFG_AHB_CLK					33

#define GCC_GPU_GPLL0_CLK_SRC					34

#define GCC_GPU_GPLL0_DIV_CLK_SRC				35

#define GCC_GPU_MEMNOC_GFX_CLK					36

#define GCC_GPU_SNOC_DVM_GFX_CLK				37

#define GCC_MSS_AXIS2_CLK					38

#define GCC_MSS_CFG_AHB_CLK					39

#define GCC_MSS_GPLL0_DIV_CLK_SRC				40

#define GCC_MSS_MFAB_AXIS_CLK					41

#define GCC_MSS_Q6_MEMNOC_AXI_CLK				42

#define GCC_MSS_SNOC_AXI_CLK					43

#define GCC_PCIE_0_AUX_CLK					44

#define GCC_PCIE_0_AUX_CLK_SRC					45

#define GCC_PCIE_0_CFG_AHB_CLK					46

#define GCC_PCIE_0_CLKREF_CLK					47

#define GCC_PCIE_0_MSTR_AXI_CLK					48

#define GCC_PCIE_0_PIPE_CLK					49

#define GCC_PCIE_0_SLV_AXI_CLK					50

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				51

#define GCC_PCIE_1_AUX_CLK					52

#define GCC_PCIE_1_AUX_CLK_SRC					53

#define GCC_PCIE_1_CFG_AHB_CLK					54

#define GCC_PCIE_1_CLKREF_CLK					55

#define GCC_PCIE_1_MSTR_AXI_CLK					56

#define GCC_PCIE_1_PIPE_CLK					57

#define GCC_PCIE_1_SLV_AXI_CLK					58

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				59

#define GCC_PCIE_PHY_AUX_CLK					60

#define GCC_PCIE_PHY_REFGEN_CLK					61

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				62

#define GCC_PDM2_CLK						63

#define GCC_PDM2_CLK_SRC					64

#define GCC_PDM_AHB_CLK						65

#define GCC_PDM_XO4_CLK						66

#define GCC_PRNG_AHB_CLK					67

#define GCC_QMIP_CAMERA_AHB_CLK					68

#define GCC_QMIP_DISP_AHB_CLK					69

#define GCC_QMIP_VIDEO_AHB_CLK					70

#define GCC_QUPV3_WRAP0_S0_CLK					71

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				72

#define GCC_QUPV3_WRAP0_S1_CLK					73

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				74

#define GCC_QUPV3_WRAP0_S2_CLK					75

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				76

#define GCC_QUPV3_WRAP0_S3_CLK					77

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				78

#define GCC_QUPV3_WRAP0_S4_CLK					79

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				80

#define GCC_QUPV3_WRAP0_S5_CLK					81

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				82

#define GCC_QUPV3_WRAP0_S6_CLK					83

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				84

#define GCC_QUPV3_WRAP0_S7_CLK					85

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				86

#define GCC_QUPV3_WRAP1_S0_CLK					87

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				88

#define GCC_QUPV3_WRAP1_S1_CLK					89

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				90

#define GCC_QUPV3_WRAP1_S2_CLK					91

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				92

#define GCC_QUPV3_WRAP1_S3_CLK					93

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				94

#define GCC_QUPV3_WRAP1_S4_CLK					95

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				96

#define GCC_QUPV3_WRAP1_S5_CLK					97

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				98

#define GCC_QUPV3_WRAP1_S6_CLK					99

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				100

#define GCC_QUPV3_WRAP1_S7_CLK					101

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				102

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				103

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				104

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				105

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				106

#define GCC_RX1_USB2_CLKREF_CLK					107

#define GCC_RX2_QLINK_CLKREF_CLK				108

#define GCC_SDCC2_AHB_CLK					109

#define GCC_SDCC2_APPS_CLK					110

#define GCC_SDCC2_APPS_CLK_SRC					111

#define GCC_SDCC4_AHB_CLK					112

#define GCC_SDCC4_APPS_CLK					113

#define GCC_SDCC4_APPS_CLK_SRC					114

#define GCC_SYS_NOC_CPUSS_AHB_CLK				115

#define GCC_TSIF_AHB_CLK					116

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				117

#define GCC_TSIF_REF_CLK					118

#define GCC_TSIF_REF_CLK_SRC					119

#define GCC_UFS_CARD_AHB_CLK					120

#define GCC_UFS_CARD_AXI_CLK					121

#define GCC_UFS_CARD_AXI_CLK_SRC				122

#define GCC_UFS_CARD_CLKREF_CLK					123

#define GCC_UFS_CARD_ICE_CORE_CLK				124

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				125

#define GCC_UFS_CARD_PHY_AUX_CLK				126

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				127

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				128

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				129

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				130

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				131

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			132

#define GCC_UFS_MEM_CLKREF_CLK					133

#define GCC_UFS_PHY_AHB_CLK					134

#define GCC_UFS_PHY_AXI_CLK					135

#define GCC_UFS_PHY_AXI_CLK_SRC					136

#define GCC_UFS_PHY_ICE_CORE_CLK				137

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				138

#define GCC_UFS_PHY_PHY_AUX_CLK					139

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				140

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				141

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				142

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				143

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				144

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				145

#define GCC_USB30_PRIM_MASTER_CLK				146

#define GCC_USB30_PRIM_MASTER_CLK_SRC				147

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				148

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			149

#define GCC_USB30_PRIM_SLEEP_CLK				150

#define GCC_USB30_SEC_MASTER_CLK				151

#define GCC_USB30_SEC_MASTER_CLK_SRC				152

#define GCC_USB30_SEC_MOCK_UTMI_CLK				153

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				154

#define GCC_USB30_SEC_SLEEP_CLK					155

#define GCC_USB3_PRIM_CLKREF_CLK				156

#define GCC_USB3_PRIM_PHY_AUX_CLK				157

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				158

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				159

#define GCC_USB3_PRIM_PHY_PIPE_CLK				160

#define GCC_USB3_SEC_CLKREF_CLK					161

#define GCC_USB3_SEC_PHY_AUX_CLK				162

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				163

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				164

#define GCC_USB3_SEC_PHY_PIPE_CLK				165

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				166

#define GCC_VIDEO_AHB_CLK					167

#define GCC_VIDEO_AXI_CLK					168

#define GCC_VIDEO_XO_CLK					169

#define GPLL0							170

#define GPLL0_OUT_EVEN						171

#define GPLL0_OUT_MAIN						172

#define GPLL1							173

#define GPLL1_OUT_MAIN						174

#define GCC_DDRSS_GPU_AXI_CLK					20

#define GCC_DISP_AHB_CLK					21

#define GCC_DISP_AXI_CLK					22

#define GCC_DISP_GPLL0_CLK_SRC					23

#define GCC_DISP_GPLL0_DIV_CLK_SRC				24

#define GCC_DISP_XO_CLK						25

#define GCC_GP1_CLK						26

#define GCC_GP1_CLK_SRC						27

#define GCC_GP2_CLK						28

#define GCC_GP2_CLK_SRC						29

#define GCC_GP3_CLK						30

#define GCC_GP3_CLK_SRC						31

#define GCC_GPU_CFG_AHB_CLK					32

#define GCC_GPU_GPLL0_CLK_SRC					33

#define GCC_GPU_GPLL0_DIV_CLK_SRC				34

#define GCC_GPU_MEMNOC_GFX_CLK					35

#define GCC_GPU_SNOC_DVM_GFX_CLK				36

#define GCC_MSS_AXIS2_CLK					37

#define GCC_MSS_CFG_AHB_CLK					38

#define GCC_MSS_GPLL0_DIV_CLK_SRC				39

#define GCC_MSS_MFAB_AXIS_CLK					40

#define GCC_MSS_Q6_MEMNOC_AXI_CLK				41

#define GCC_MSS_SNOC_AXI_CLK					42

#define GCC_PCIE_0_AUX_CLK					43

#define GCC_PCIE_0_AUX_CLK_SRC					44

#define GCC_PCIE_0_CFG_AHB_CLK					45

#define GCC_PCIE_0_CLKREF_CLK					46

#define GCC_PCIE_0_MSTR_AXI_CLK					47

#define GCC_PCIE_0_PIPE_CLK					48

#define GCC_PCIE_0_SLV_AXI_CLK					49

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				50

#define GCC_PCIE_1_AUX_CLK					51

#define GCC_PCIE_1_AUX_CLK_SRC					52

#define GCC_PCIE_1_CFG_AHB_CLK					53

#define GCC_PCIE_1_CLKREF_CLK					54

#define GCC_PCIE_1_MSTR_AXI_CLK					55

#define GCC_PCIE_1_PIPE_CLK					56

#define GCC_PCIE_1_SLV_AXI_CLK					57

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				58

#define GCC_PCIE_PHY_AUX_CLK					59

#define GCC_PCIE_PHY_REFGEN_CLK					60

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				61

#define GCC_PDM2_CLK						62

#define GCC_PDM2_CLK_SRC					63

#define GCC_PDM_AHB_CLK						64

#define GCC_PDM_XO4_CLK						65

#define GCC_PRNG_AHB_CLK					66

#define GCC_QMIP_CAMERA_AHB_CLK					67

#define GCC_QMIP_DISP_AHB_CLK					68

#define GCC_QMIP_VIDEO_AHB_CLK					69

#define GCC_QUPV3_WRAP0_S0_CLK					70

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				71

#define GCC_QUPV3_WRAP0_S1_CLK					72

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				73

#define GCC_QUPV3_WRAP0_S2_CLK					74

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S3_CLK					76

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S4_CLK					78

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				79

#define GCC_QUPV3_WRAP0_S5_CLK					80

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S6_CLK					82

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S7_CLK					84

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				85

#define GCC_QUPV3_WRAP1_S0_CLK					86

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				87

#define GCC_QUPV3_WRAP1_S1_CLK					88

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				89

#define GCC_QUPV3_WRAP1_S2_CLK					90

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				91

#define GCC_QUPV3_WRAP1_S3_CLK					92

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S4_CLK					94

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S5_CLK					96

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S6_CLK					98

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S7_CLK					100

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				101

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				102

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				103

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				104

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				105

#define GCC_SDCC2_AHB_CLK					106

#define GCC_SDCC2_APPS_CLK					107

#define GCC_SDCC2_APPS_CLK_SRC					108

#define GCC_SDCC4_AHB_CLK					109

#define GCC_SDCC4_APPS_CLK					110

#define GCC_SDCC4_APPS_CLK_SRC					111

#define GCC_SYS_NOC_CPUSS_AHB_CLK				112

#define GCC_TSIF_AHB_CLK					113

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				114

#define GCC_TSIF_REF_CLK					115

#define GCC_TSIF_REF_CLK_SRC					116

#define GCC_UFS_CARD_AHB_CLK					117

#define GCC_UFS_CARD_AXI_CLK					118

#define GCC_UFS_CARD_AXI_CLK_SRC				119

#define GCC_UFS_CARD_CLKREF_CLK					120

#define GCC_UFS_CARD_ICE_CORE_CLK				121

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				122

#define GCC_UFS_CARD_PHY_AUX_CLK				123

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				124

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				125

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				126

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				127

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				128

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			129

#define GCC_UFS_MEM_CLKREF_CLK					130

#define GCC_UFS_PHY_AHB_CLK					131

#define GCC_UFS_PHY_AXI_CLK					132

#define GCC_UFS_PHY_AXI_CLK_SRC					133

#define GCC_UFS_PHY_ICE_CORE_CLK				134

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				135

#define GCC_UFS_PHY_PHY_AUX_CLK					136

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				137

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				138

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				139

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				140

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				141

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				142

#define GCC_USB30_PRIM_MASTER_CLK				143

#define GCC_USB30_PRIM_MASTER_CLK_SRC				144

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				145

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			146

#define GCC_USB30_PRIM_SLEEP_CLK				147

#define GCC_USB30_SEC_MASTER_CLK				148

#define GCC_USB30_SEC_MASTER_CLK_SRC				149

#define GCC_USB30_SEC_MOCK_UTMI_CLK				150

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				151

#define GCC_USB30_SEC_SLEEP_CLK					152

#define GCC_USB3_PRIM_CLKREF_CLK				153

#define GCC_USB3_PRIM_PHY_AUX_CLK				154

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				155

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				156

#define GCC_USB3_PRIM_PHY_PIPE_CLK				157

#define GCC_USB3_SEC_CLKREF_CLK					158

#define GCC_USB3_SEC_PHY_AUX_CLK				159

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				160

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				161

#define GCC_USB3_SEC_PHY_PIPE_CLK				162

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				163

#define GCC_VIDEO_AHB_CLK					164

#define GCC_VIDEO_AXI_CLK					165

#define GCC_VIDEO_XO_CLK					166

#define GPLL0							167

#define GPLL0_OUT_EVEN						168

#define GPLL0_OUT_MAIN						169

#define GPLL1							170

#define GPLL1_OUT_MAIN						171



/* GCC reset clocks */

#define GCC_GPU_BCR						0