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Commit afc85918 authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Add back part of VBIF soft reset registers 



These were removed from the A6XX patch adding GMU support.
Add them back in so soft reset could possibly work in the
generic Adreno soft reset path.

Change-Id: Ib55c685bca4d69fe70184e3eda0add07169c6fa0
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent 492b05c7

drivers/gpu/msm/a6xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -710,6 +710,7 @@ 
#define A6XX_VBIF_VERSION                       0x3000

#define A6XX_VBIF_GATE_OFF_WRREQ_EN             0x302A

#define A6XX_VBIF_XIN_HALT_CTRL0                0x3080

#define A6XX_VBIF_XIN_HALT_CTRL0_MASK           0xF

#define A6XX_VBIF_XIN_HALT_CTRL1                0x3081

#define A6XX_VBIF_PERF_CNT_SEL0                 0x30d0

#define A6XX_VBIF_PERF_CNT_SEL1                 0x30d1

drivers/gpu/msm/adreno_a6xx.c

+6 −0
Original line number Diff line number Diff line
@@ -217,11 +217,13 @@ static struct a6xx_protected_regs { 
static void a6xx_platform_setup(struct adreno_device *adreno_dev)

{

	uint64_t addr;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	/* Calculate SP local and private mem addresses */

	addr = ALIGN(ADRENO_UCHE_GMEM_BASE + adreno_dev->gmem_size, SZ_64K);

	adreno_dev->sp_local_gpuaddr = addr;

	adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K;

	gpudev->vbif_xin_halt_ctrl0_mask = A6XX_VBIF_XIN_HALT_CTRL0_MASK;

}



static void _update_always_on_regs(struct adreno_device *adreno_dev)
@@ -2228,6 +2230,10 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

				A6XX_RBBM_PERFCTR_LOAD_VALUE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION, A6XX_VBIF_VERSION),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL0,

				A6XX_VBIF_XIN_HALT_CTRL0),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL1,

				A6XX_VBIF_XIN_HALT_CTRL1),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,

				A6XX_GMU_ALWAYS_ON_COUNTER_L),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI,