Loading arch/arm64/boot/dts/qcom/sdm845.dtsi +32 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ #include <dt-bindings/soc/qcom,tcs-mbox.h> #include <dt-bindings/spmi/spmi.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/msm/msm-bus-ids.h> / { model = "Qualcomm Technologies, Inc. SDM845"; Loading Loading @@ -800,6 +801,37 @@ qcom,target-dev = <&cpubw>; }; llccbw: qcom,llccbw { compatible = "qcom,devbw"; governor = "powersave"; qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; qcom,active-only; qcom,bw-tbl = < 762 /* 200 MHz */ >, < 1144 /* 300 MHz */ >, < 1720 /* 451 MHz */ >, < 2086 /* 547 MHz */ >, < 2597 /* 681 MHz */ >, < 2929 /* 768 MHz */ >, < 3879 /* 1017 MHz */ >, < 4943 /* 1296 MHz */ >, < 5931 /* 1555 MHz */ >, < 6881 /* 1804 MHz */ >; }; llcc_bwmon: qcom,llcc-bwmon { compatible = "qcom,bimc-bwmon5"; reg = <0x0114A000 0x1000>; reg-names = "base"; interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&llccbw>; qcom,count-unit = <0x400000>; qcom,byte-mid-mask = <0xe000>; qcom,byte-mid-match = <0xe000>; }; memlat_cpu0: qcom,memlat-cpu0 { compatible = "qcom,devbw"; governor = "powersave"; Loading Loading
arch/arm64/boot/dts/qcom/sdm845.dtsi +32 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,7 @@ #include <dt-bindings/soc/qcom,tcs-mbox.h> #include <dt-bindings/spmi/spmi.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/msm/msm-bus-ids.h> / { model = "Qualcomm Technologies, Inc. SDM845"; Loading Loading @@ -800,6 +801,37 @@ qcom,target-dev = <&cpubw>; }; llccbw: qcom,llccbw { compatible = "qcom,devbw"; governor = "powersave"; qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; qcom,active-only; qcom,bw-tbl = < 762 /* 200 MHz */ >, < 1144 /* 300 MHz */ >, < 1720 /* 451 MHz */ >, < 2086 /* 547 MHz */ >, < 2597 /* 681 MHz */ >, < 2929 /* 768 MHz */ >, < 3879 /* 1017 MHz */ >, < 4943 /* 1296 MHz */ >, < 5931 /* 1555 MHz */ >, < 6881 /* 1804 MHz */ >; }; llcc_bwmon: qcom,llcc-bwmon { compatible = "qcom,bimc-bwmon5"; reg = <0x0114A000 0x1000>; reg-names = "base"; interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; qcom,hw-timer-hz = <19200000>; qcom,target-dev = <&llccbw>; qcom,count-unit = <0x400000>; qcom,byte-mid-mask = <0xe000>; qcom,byte-mid-match = <0xe000>; }; memlat_cpu0: qcom,memlat-cpu0 { compatible = "qcom,devbw"; governor = "powersave"; Loading