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Commit aed6ec79 authored by Rajesh Kemisetti's avatar Rajesh Kemisetti Committed by Lynus Vaz
Browse files

msm: kgsl: Add support for A508 GPU on SDM630 



Add new GPU ID: A508 and corresponding VBIF and initial
settings on SDM630.

Change-Id: If1cd782beb50098a69a9d05acb083ef4b0465766
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
parent bfd1eb97

drivers/gpu/msm/adreno-gpulist.h

+16 −0
Original line number Diff line number Diff line
@@ -304,6 +304,22 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A508,

		.core = 5,

		.major = 0,

		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a508_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = (SZ_128K + SZ_8K),

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A630,

		.core = 6,

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A430 = 430,

	ADRENO_REV_A505 = 505,

	ADRENO_REV_A506 = 506,

	ADRENO_REV_A508 = 508,

	ADRENO_REV_A510 = 510,

	ADRENO_REV_A512 = 512,

	ADRENO_REV_A530 = 530,
@@ -1022,6 +1023,7 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) 


ADRENO_TARGET(a505, ADRENO_REV_A505)

ADRENO_TARGET(a506, ADRENO_REV_A506)

ADRENO_TARGET(a508, ADRENO_REV_A508)

ADRENO_TARGET(a510, ADRENO_REV_A510)

ADRENO_TARGET(a512, ADRENO_REV_A512)

ADRENO_TARGET(a530, ADRENO_REV_A530)

drivers/gpu/msm/adreno_a5xx.c

+8 −5
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ static const struct adreno_vbif_platform a5xx_vbif_platforms[] = { 
	{ adreno_is_a530, a530_vbif },

	{ adreno_is_a512, a540_vbif },

	{ adreno_is_a510, a530_vbif },

	{ adreno_is_a508, a530_vbif },

	{ adreno_is_a505, a530_vbif },

	{ adreno_is_a506, a530_vbif },

};
@@ -180,7 +181,7 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
	uint64_t addr;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	if (adreno_is_a505_or_a506(adreno_dev)) {

	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {

		gpudev->snapshot_data->sect_sizes->cp_meq = 32;

		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;

		gpudev->snapshot_data->sect_sizes->roq = 256;
@@ -536,7 +537,7 @@ static void a5xx_regulator_disable(struct adreno_device *adreno_dev) 
	unsigned int reg;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (adreno_is_a512(adreno_dev))

	if (adreno_is_a512(adreno_dev) || adreno_is_a508(adreno_dev))

		return;



	/* If feature is not supported or not enabled */
@@ -1194,6 +1195,7 @@ static const struct { 
	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

	{ adreno_is_a505, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a506, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

	{ adreno_is_a508, a50x_hwcg_regs, ARRAY_SIZE(a50x_hwcg_regs) },

};



void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
@@ -1638,7 +1640,8 @@ static void a5xx_clk_set_options(struct adreno_device *adreno_dev, 
	const char *name, struct clk *clk)

{

	/* Handle clock settings for GFX PSCBCs */

	if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev)) {

	if (adreno_is_a540(adreno_dev) || adreno_is_a512(adreno_dev) ||

		adreno_is_a508(adreno_dev)) {

		if (!strcmp(name, "mem_iface_clk")) {

			clk_set_flags(clk, CLKFLAG_NORETAIN_PERIPH);

			clk_set_flags(clk, CLKFLAG_NORETAIN_MEM);
@@ -1925,7 +1928,7 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	 * Below CP registers are 0x0 by default, program init

	 * values based on a5xx flavor.

	 */

	if (adreno_is_a505_or_a506(adreno_dev)) {

	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x20);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
@@ -1951,7 +1954,7 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	 * vtxFifo and primFifo thresholds default values

	 * are different.

	 */

	if (adreno_is_a505_or_a506(adreno_dev))

	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev))

		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x100 << 11 | 0x100 << 22));

	else if (adreno_is_a510(adreno_dev) || adreno_is_a512(adreno_dev))