Loading arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi 0 → 100644 +43 −0 Original line number Diff line number Diff line /* * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ] * * Copyright 2012 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ message@42400 { compatible = "fsl,mpic-v3.1-msgr"; reg = <0x42400 0x200>; interrupts = < 0xb4 2 0 0 0xb5 2 0 0 0xb6 2 0 0 0xb7 2 0 0>; }; arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -53,6 +53,16 @@ timer@41100 { 3 0 3 0>; }; message@41400 { compatible = "fsl,mpic-v3.1-msgr"; reg = <0x41400 0x200>; interrupts = < 0xb0 2 0 0 0xb1 2 0 0 0xb2 2 0 0 0xb3 2 0 0>; }; msi@41600 { compatible = "fsl,mpic-msi"; reg = <0x41600 0x80>; Loading arch/powerpc/include/asm/mpic_msgr.h +1 −0 Original line number Diff line number Diff line Loading @@ -13,6 +13,7 @@ #include <linux/types.h> #include <linux/spinlock.h> #include <asm/smp.h> struct mpic_msgr { u32 __iomem *base; Loading arch/powerpc/include/asm/reg_booke.h +0 −5 Original line number Diff line number Diff line Loading @@ -15,11 +15,6 @@ #ifndef __ASM_POWERPC_REG_BOOKE_H__ #define __ASM_POWERPC_REG_BOOKE_H__ #ifdef CONFIG_BOOKE_WDT extern u32 booke_wdt_enabled; extern u32 booke_wdt_period; #endif /* CONFIG_BOOKE_WDT */ /* Machine State Register (MSR) Fields */ #define MSR_GS (1<<28) /* Guest state */ #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ Loading arch/powerpc/kernel/setup_32.c +3 −0 Original line number Diff line number Diff line Loading @@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr) } #ifdef CONFIG_BOOKE_WDT extern u32 booke_wdt_enabled; extern u32 booke_wdt_period; /* Checks wdt=x and wdt_period=xx command-line option */ notrace int __init early_parse_wdt(char *p) { Loading Loading
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi 0 → 100644 +43 −0 Original line number Diff line number Diff line /* * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ] * * Copyright 2012 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ message@42400 { compatible = "fsl,mpic-v3.1-msgr"; reg = <0x42400 0x200>; interrupts = < 0xb4 2 0 0 0xb5 2 0 0 0xb6 2 0 0 0xb7 2 0 0>; };
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -53,6 +53,16 @@ timer@41100 { 3 0 3 0>; }; message@41400 { compatible = "fsl,mpic-v3.1-msgr"; reg = <0x41400 0x200>; interrupts = < 0xb0 2 0 0 0xb1 2 0 0 0xb2 2 0 0 0xb3 2 0 0>; }; msi@41600 { compatible = "fsl,mpic-msi"; reg = <0x41600 0x80>; Loading
arch/powerpc/include/asm/mpic_msgr.h +1 −0 Original line number Diff line number Diff line Loading @@ -13,6 +13,7 @@ #include <linux/types.h> #include <linux/spinlock.h> #include <asm/smp.h> struct mpic_msgr { u32 __iomem *base; Loading
arch/powerpc/include/asm/reg_booke.h +0 −5 Original line number Diff line number Diff line Loading @@ -15,11 +15,6 @@ #ifndef __ASM_POWERPC_REG_BOOKE_H__ #define __ASM_POWERPC_REG_BOOKE_H__ #ifdef CONFIG_BOOKE_WDT extern u32 booke_wdt_enabled; extern u32 booke_wdt_period; #endif /* CONFIG_BOOKE_WDT */ /* Machine State Register (MSR) Fields */ #define MSR_GS (1<<28) /* Guest state */ #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ Loading
arch/powerpc/kernel/setup_32.c +3 −0 Original line number Diff line number Diff line Loading @@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr) } #ifdef CONFIG_BOOKE_WDT extern u32 booke_wdt_enabled; extern u32 booke_wdt_period; /* Checks wdt=x and wdt_period=xx command-line option */ notrace int __init early_parse_wdt(char *p) { Loading