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Commit aeb94eb2 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Narendra Muppalla
Browse files

clk: msm: mdss: change DP clock rate in order of KHz 



Certain frequencies of DP VCO clock are more than 4.29 GHz
and are not supported by clock framework on 32 bit builds,
since it exceeds the maximum value of unsigned long data type.
To fix this issue, change the DP link clock frequencies in order
of KHz in DP FB driver/MMSS 8998 clock driver/DP PLL driver.

Change-Id: I46d9b5c57f94aa1f10df08c4430b617355a82eec
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: default avatarNarendra Muppalla <narendram@codeaurora.org>
parent e95883b0

drivers/clk/qcom/mdss/mdss-dp-pll-8998-util.c

+17 −17
Original line number Diff line number Diff line
@@ -190,9 +190,9 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) 
			QSERDES_COM_CLK_SEL, 0x30);



	/* Different for each clock rates */

	if (rate == DP_VCO_HSCLK_RATE_1620MHz) {

		pr_debug("%s: VCO rate: %lld\n", __func__,

				DP_VCO_RATE_8100MHz);

	if (rate == DP_VCO_HSCLK_RATE_1620MHZDIV1000) {

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_8100MHZDIV1000);

		MDSS_PLL_REG_W(dp_res->pll_base,

			QSERDES_COM_SYS_CLK_CTRL, 0x02);

		MDSS_PLL_REG_W(dp_res->pll_base,
@@ -215,9 +215,9 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) 
			QSERDES_COM_LOCK_CMP2_MODE0, 0x21);

		MDSS_PLL_REG_W(dp_res->pll_base,

			QSERDES_COM_LOCK_CMP3_MODE0, 0x00);

	} else if (rate == DP_VCO_HSCLK_RATE_2700MHz) {

		pr_debug("%s: VCO rate: %lld\n", __func__,

				DP_VCO_RATE_8100MHz);

	} else if (rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000) {

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_8100MHZDIV1000);

		MDSS_PLL_REG_W(dp_res->pll_base,

			QSERDES_COM_SYS_CLK_CTRL, 0x06);

		MDSS_PLL_REG_W(dp_res->pll_base,
@@ -240,9 +240,9 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) 
			QSERDES_COM_LOCK_CMP2_MODE0, 0x38);

		MDSS_PLL_REG_W(dp_res->pll_base,

			QSERDES_COM_LOCK_CMP3_MODE0, 0x00);

	} else if (rate == DP_VCO_HSCLK_RATE_5400MHz) {

		pr_debug("%s: VCO rate: %lld\n", __func__,

				DP_VCO_RATE_10800MHz);

	} else if (rate == DP_VCO_HSCLK_RATE_5400MHZDIV1000) {

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_10800MHZDIV1000);

		MDSS_PLL_REG_W(dp_res->pll_base,

			QSERDES_COM_SYS_CLK_CTRL, 0x06);

		MDSS_PLL_REG_W(dp_res->pll_base,
@@ -272,8 +272,8 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) 
	/* Make sure the PLL register writes are done */

	wmb();



	if ((rate == DP_VCO_HSCLK_RATE_1620MHz)

	    || (rate == DP_VCO_HSCLK_RATE_2700MHz)) {

	if ((rate == DP_VCO_HSCLK_RATE_1620MHZDIV1000)

	    || (rate == DP_VCO_HSCLK_RATE_2700MHZDIV1000)) {

		MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_VCO_DIV, 0x1);

	} else {
@@ -713,14 +713,14 @@ unsigned long dp_vco_get_rate(struct clk *c) 
		pr_err("%s: unsupported div. Phy_mode: %d\n", __func__, div);



	if (link2xclk_div == 10) {

		vco_rate = DP_VCO_HSCLK_RATE_2700MHz;

		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	} else {

		if (hsclk_div == 5)

			vco_rate = DP_VCO_HSCLK_RATE_1620MHz;

			vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000;

		else if (hsclk_div == 3)

			vco_rate = DP_VCO_HSCLK_RATE_2700MHz;

			vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

		else

			vco_rate = DP_VCO_HSCLK_RATE_5400MHz;

			vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;

	}



	pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);
@@ -737,8 +737,8 @@ long dp_vco_round_rate(struct clk *c, unsigned long rate) 


	if (rate <= vco->min_rate)

		rrate = vco->min_rate;

	else if (rate <= DP_VCO_HSCLK_RATE_2700MHz)

		rrate = DP_VCO_HSCLK_RATE_2700MHz;

	else if (rate <= DP_VCO_HSCLK_RATE_2700MHZDIV1000)

		rrate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	else

		rrate = vco->max_rate;

drivers/clk/qcom/mdss/mdss-dp-pll-8998.c

+2 −2
Original line number Diff line number Diff line
@@ -93,8 +93,8 @@ static struct clk_mux_ops mdss_mux_ops = { 
};



static struct dp_pll_vco_clk dp_vco_clk = {

	.min_rate = DP_VCO_HSCLK_RATE_1620MHz,

	.max_rate = DP_VCO_HSCLK_RATE_5400MHz,

	.min_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000,

	.max_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000,

	.c = {

		.dbg_name = "dp_vco_clk",

		.ops = &dp_8998_vco_clk_ops,

drivers/clk/qcom/mdss/mdss-dp-pll-8998.h

+6 −6
Original line number Diff line number Diff line 
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -155,12 +155,12 @@ 
#define DP_PLL_POLL_SLEEP_US			500

#define DP_PLL_POLL_TIMEOUT_US			10000



#define DP_VCO_RATE_8100MHz			8100000000ULL

#define DP_VCO_RATE_10800MHz			10800000000ULL

#define DP_VCO_RATE_8100MHZDIV1000		8100000UL

#define DP_VCO_RATE_10800MHZDIV1000		10800000UL



#define DP_VCO_HSCLK_RATE_1620MHz		1620000000ULL

#define DP_VCO_HSCLK_RATE_2700MHz		2700000000ULL

#define DP_VCO_HSCLK_RATE_5400MHz		5400000000ULL

#define DP_VCO_HSCLK_RATE_1620MHZDIV1000	1620000UL

#define DP_VCO_HSCLK_RATE_2700MHZDIV1000	2700000UL

#define DP_VCO_HSCLK_RATE_5400MHZDIV1000	5400000UL



int dp_vco_set_rate(struct clk *c, unsigned long rate);

unsigned long dp_vco_get_rate(struct clk *c);