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Commit aeb8f8cb authored by Chris Brandt's avatar Chris Brandt Committed by Mark Brown
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spi: rspi: Increase accuracy of bit rate for RZ 



When you leave the clock divider at 0, 130kHz is the lowest you can go.
Also, by adjusting the clock divider you can get more accurate resolutions
for clock speeds lower than 16MHz. This patch uses the clock divider as
part of the bit rate setup.

Signed-off-by: default avatarChris Brandt <chris.brandt@renesas.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 29b4817d

drivers/spi/spi-rspi.c

+12 −2
Original line number Diff line number Diff line
@@ -295,14 +295,24 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 
static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)

{

	int spbr;

	int div = 0;

	unsigned long clksrc;



	/* Sets output mode, MOSI signal, and (optionally) loopback */

	rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);



	clksrc = clk_get_rate(rspi->clk);

	while (div < 3) {

		if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */

			break;

		div++;

		clksrc /= 2;

	}



	/* Sets transfer bit rate */

	spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),

			    2 * rspi->max_speed_hz) - 1;

	spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;

	rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);

	rspi->spcmd |= div << 2;



	/* Disable dummy transmission, set byte access */

	rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);