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Commit aea22a0f authored by Vicky Wallace's avatar Vicky Wallace Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add GCC driver support for sdxpoorwills 



Add support for peripheral clocks frequency plan.

CRs-Fixed: 2143381
Change-Id: I3c84dc59a18f3f07e13097abd273c21fbaec7d38
Signed-off-by: default avatarVicky Wallace <vwallace@codeaurora.org>
parent 82b6461b

Documentation/devicetree/bindings/clock/qcom,gcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ Required properties : 
			"qcom,gcc-sdm845-v2.1"

			"qcom,gcc-sdm670"

			"qcom,debugcc-sdm845"

			"qcom,gcc-sdxpoorwills"



- reg : shall contain base register location and length

- #clock-cells : shall contain 1

drivers/clk/qcom/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -235,4 +235,12 @@ config MSM_CLK_AOP_QMP 
	subsystems via QMP mailboxes.

	Say Y to support the clocks managed by AOP on platforms such as sdm845.



config MDM_GCC_SDXPOORWILLS

	tristate "SDXPOORWILLS Global Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the global clock controller on sdxpoorwills devices.

	  Say Y if you want to use peripheral devices such as UART, SPI,

	  i2c, USB, SD/eMMC, etc.



source "drivers/clk/qcom/mdss/Kconfig"

drivers/clk/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o 
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o

obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o

obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o

obj-$(CONFIG_MDM_GCC_SDXPOORWILLS) += gcc-sdxpoorwills.o

obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o

obj-$(CONFIG_MSM_CAMCC_SDM845) += camcc-sdm845.o

obj-$(CONFIG_MSM_CLK_AOP_QMP) += clk-aop-qmp.o

drivers/clk/qcom/gcc-sdxpoorwills.c

0 → 100644
+1916 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,gcc-sdxpoorwills.h

+55 −53
Original line number Diff line number Diff line
@@ -48,59 +48,60 @@ 
#define GCC_CPUSS_AHB_CLK					30

#define GCC_CPUSS_AHB_CLK_SRC					31

#define GCC_CPUSS_GNOC_CLK					32

#define GCC_CPUSS_GPLL0_CLK_SRC					33

#define GCC_CPUSS_RBCPR_CLK					34

#define GCC_CPUSS_RBCPR_CLK_SRC					35

#define GCC_GP1_CLK						36

#define GCC_GP1_CLK_SRC						37

#define GCC_GP2_CLK						38

#define GCC_GP2_CLK_SRC						39

#define GCC_GP3_CLK						40

#define GCC_GP3_CLK_SRC						41

#define GCC_MSS_CFG_AHB_CLK					42

#define GCC_MSS_GPLL0_DIV_CLK_SRC				43

#define GCC_MSS_SNOC_AXI_CLK					44

#define GCC_PCIE_AUX_CLK					45

#define GCC_PCIE_AUX_PHY_CLK_SRC				46

#define GCC_PCIE_CFG_AHB_CLK					47

#define GCC_PCIE_0_CLKREF_EN					48

#define GCC_PCIE_MSTR_AXI_CLK					49

#define GCC_PCIE_PHY_REFGEN_CLK					50

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				51

#define GCC_PCIE_PIPE_CLK					52

#define GCC_PCIE_SLEEP_CLK					53

#define GCC_PCIE_SLV_AXI_CLK					54

#define GCC_PCIE_SLV_Q2A_AXI_CLK				55

#define GCC_PDM2_CLK						56

#define GCC_PDM2_CLK_SRC					57

#define GCC_PDM_AHB_CLK						58

#define GCC_PDM_XO4_CLK						59

#define GCC_PRNG_AHB_CLK					60

#define GCC_SDCC1_AHB_CLK					61

#define GCC_SDCC1_APPS_CLK					62

#define GCC_SDCC1_APPS_CLK_SRC					63

#define GCC_SPMI_FETCHER_AHB_CLK				64

#define GCC_SPMI_FETCHER_CLK					65

#define GCC_SPMI_FETCHER_CLK_SRC				66

#define GCC_SYS_NOC_CPUSS_AHB_CLK				67

#define GCC_SYS_NOC_USB3_CLK					68

#define GCC_USB30_MASTER_CLK					69

#define GCC_USB30_MASTER_CLK_SRC				70

#define GCC_USB30_MOCK_UTMI_CLK					71

#define GCC_USB30_MOCK_UTMI_CLK_SRC				72

#define GCC_USB30_SLEEP_CLK					73

#define GCC_USB3_PRIM_CLKREF_CLK				74

#define GCC_USB3_PHY_AUX_CLK					75

#define GCC_USB3_PHY_AUX_CLK_SRC				76

#define GCC_USB3_PHY_PIPE_CLK					77

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				78

#define GCC_XO_DIV4_CLK						79

#define GPLL0							80

#define GPLL0_OUT_EVEN						81



/* GDSCs */

#define PCIE_GDSC						0

#define USB30_GDSC						1

#define GCC_CPUSS_RBCPR_CLK					33

#define GCC_CPUSS_RBCPR_CLK_SRC					34

#define GCC_EMAC_CLK_SRC					35

#define GCC_EMAC_PTP_CLK_SRC					36

#define GCC_ETH_AXI_CLK						37

#define GCC_ETH_PTP_CLK						38

#define GCC_ETH_RGMII_CLK					39

#define GCC_ETH_SLAVE_AHB_CLK					40

#define GCC_GP1_CLK						41

#define GCC_GP1_CLK_SRC						42

#define GCC_GP2_CLK						43

#define GCC_GP2_CLK_SRC						44

#define GCC_GP3_CLK						45

#define GCC_GP3_CLK_SRC						46

#define GCC_MSS_CFG_AHB_CLK					47

#define GCC_MSS_GPLL0_DIV_CLK_SRC				48

#define GCC_MSS_SNOC_AXI_CLK					49

#define GCC_PCIE_AUX_CLK					50

#define GCC_PCIE_AUX_PHY_CLK_SRC				51

#define GCC_PCIE_CFG_AHB_CLK					52

#define GCC_PCIE_MSTR_AXI_CLK					53

#define GCC_PCIE_PHY_REFGEN_CLK					54

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				55

#define GCC_PCIE_PIPE_CLK					56

#define GCC_PCIE_SLEEP_CLK					57

#define GCC_PCIE_SLV_AXI_CLK					58

#define GCC_PCIE_SLV_Q2A_AXI_CLK				59

#define GCC_PDM2_CLK						60

#define GCC_PDM2_CLK_SRC					61

#define GCC_PDM_AHB_CLK						62

#define GCC_PDM_XO4_CLK						63

#define GCC_PRNG_AHB_CLK					64

#define GCC_SDCC1_AHB_CLK					65

#define GCC_SDCC1_APPS_CLK					66

#define GCC_SDCC1_APPS_CLK_SRC					67

#define GCC_SPMI_FETCHER_AHB_CLK				68

#define GCC_SPMI_FETCHER_CLK					69

#define GCC_SPMI_FETCHER_CLK_SRC				70

#define GCC_SYS_NOC_CPUSS_AHB_CLK				71

#define GCC_SYS_NOC_USB3_CLK					72

#define GCC_USB30_MASTER_CLK					73

#define GCC_USB30_MASTER_CLK_SRC				74

#define GCC_USB30_MOCK_UTMI_CLK					75

#define GCC_USB30_MOCK_UTMI_CLK_SRC				76

#define GCC_USB30_SLEEP_CLK					77

#define GCC_USB3_PHY_AUX_CLK					78

#define GCC_USB3_PHY_AUX_CLK_SRC				79

#define GCC_USB3_PHY_PIPE_CLK					80

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				81

#define GPLL0							82

#define GPLL0_OUT_EVEN						83

#define GPLL4							84

#define GPLL4_OUT_EVEN						85

#define GCC_USB3_PRIM_CLKREF_CLK				86



/* CPU clocks */

#define CLOCK_A7SS						0
@@ -125,5 +126,6 @@ 
#define GCC_USB3PHY_PHY_BCR					16

#define GCC_QUSB2PHY_BCR					17

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				18

#define GCC_EMAC_BCR						19



#endif