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Commit ae60b992 authored by Vidyakumar Athota's avatar Vidyakumar Athota Committed by Gerrit - the friendly Code Review server
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ASoC: wcd934x: donot reset codec state variables during SSR



During subsystem restart compander, hph_mode, class-h and svs
state variables are reset in post reset callback which results
mismatch between software and hardware states after SSR. Avoid
resetting of these variables to reflect HW state properly.

Change-Id: I3e9c805de31405c6edddcce70a8f314612ef9196
Signed-off-by: default avatarVidyakumar Athota <vathota@codeaurora.org>
parent 5dea59a9
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+1 −14
Original line number Diff line number Diff line
@@ -8796,13 +8796,8 @@ static int tavil_post_reset_cb(struct wcd9xxx *wcd9xxx)
				WCD9XXX_DIG_CORE_REGION_1);

	mutex_lock(&tavil->codec_mutex);
	/*
	 * Codec hardware by default comes up in SVS mode.
	 * Initialize the svs_ref_cnt to 1 to reflect the hardware
	 * state in the driver.
	 */
	tavil->svs_ref_cnt = 1;

	tavil_vote_svs(tavil, true);
	tavil_slimbus_slave_port_cfg.slave_dev_intfdev_la =
				control->slim_slave->laddr;
	tavil_slimbus_slave_port_cfg.slave_dev_pgd_la =
@@ -8810,17 +8805,9 @@ static int tavil_post_reset_cb(struct wcd9xxx *wcd9xxx)
	tavil_init_slim_slave_cfg(codec);
	snd_soc_card_change_online_state(codec->component.card, 1);

	/* Class-H Init */
	wcd_clsh_init(&tavil->clsh_d);
	/* Default HPH Mode to Class-H LOHiFi */
	tavil->hph_mode = CLS_H_LOHIFI;

	for (i = 0; i < TAVIL_MAX_MICBIAS; i++)
		tavil->micb_ref[i] = 0;

	for (i = 0; i < COMPANDER_MAX; i++)
		tavil->comp_enabled[i] = 0;

	dev_dbg(codec->dev, "%s: MCLK Rate = %x\n",
		__func__, control->mclk_rate);

+7 −2
Original line number Diff line number Diff line
/*
 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
 * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -34,7 +34,12 @@
#define	WCD_CLSH_STATE_HPHL (0x01 << 1)
#define	WCD_CLSH_STATE_HPHR (0x01 << 2)
#define	WCD_CLSH_STATE_LO (0x01 << 3)
#define WCD_CLSH_STATE_MAX 4

/*
 * Though number of CLSH states are 4, max state shoulbe be 5
 * because state array index starts from 1.
 */
#define WCD_CLSH_STATE_MAX 5
#define NUM_CLSH_STATES_V2 (0x01 << WCD_CLSH_STATE_MAX)