Merge "msm: ipa: add support for new uC opcode" (ae17f5a2) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/platform/msm/ipa/ipa_api.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -172,6 +172,7 @@ const char *ipa_clients_strings[IPA_CLIENT_MAX] = {
		__stringify(IPA_CLIENT_TEST3_CONS),
		__stringify(IPA_CLIENT_TEST4_PROD),
		__stringify(IPA_CLIENT_TEST4_CONS),
		__stringify(IPA_CLIENT_DUMMY_CONS),
		};

		/**

drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -82,6 +82,8 @@ const char *ipa3_hdr_proc_type_name[] = {
		__stringify(IPA_HDR_PROC_ETHII_TO_802_3),
		__stringify(IPA_HDR_PROC_802_3_TO_ETHII),
		__stringify(IPA_HDR_PROC_802_3_TO_802_3),
		__stringify(IPA_HDR_PROC_L2TP_HEADER_ADD),
		__stringify(IPA_HDR_PROC_L2TP_HEADER_REMOVE),
		};

		static struct dentry *dent;

drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -13,7 +13,7 @@
		#include "ipa_i.h"
		#include "ipahal/ipahal.h"

		static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 24, 36, 60};
		static const u32 ipa_hdr_bin_sz[IPA_HDR_BIN_MAX] = { 8, 16, 24, 36, 64};
		static const u32 ipa_hdr_proc_ctx_bin_sz[IPA_HDR_PROC_CTX_BIN_MAX] = { 32, 64};

		#define HDR_TYPE_IS_VALID(type) \
		@@ -78,7 +78,8 @@ static int ipa3_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem,
		entry->hdr->is_hdr_proc_ctx,
		entry->hdr->phys_base,
		hdr_base_addr,
		entry->hdr->offset_entry);
		entry->hdr->offset_entry,
		entry->l2tp_params);
		if (ret)
		return ret;
		}
		@@ -353,6 +354,7 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx,

		entry->type = proc_ctx->type;
		entry->hdr = hdr_entry;
		entry->l2tp_params = proc_ctx->l2tp_params;
		if (add_ref_hdr)
		hdr_entry->ref_cnt++;
		entry->cookie = IPA_COOKIE;

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+3 −1

Original line number	Diff line number	Diff line
		@@ -322,7 +322,8 @@ struct ipa3_hdr_proc_ctx_offset_entry {
		/**
		* struct ipa3_hdr_proc_ctx_entry - IPA processing context header table entry
		* @link: entry's link in global header table entries list
		* @type:
		* @type: header processing context type
		* @l2tp_params: L2TP parameters
		* @offset_entry: entry's offset
		* @hdr: the header
		* @cookie: cookie used for validity check
		@@ -333,6 +334,7 @@ struct ipa3_hdr_proc_ctx_offset_entry {
		struct ipa3_hdr_proc_ctx_entry {
		struct list_head link;
		enum ipa_hdr_proc_type type;
		union ipa_l2tp_hdr_proc_ctx_params l2tp_params;
		struct ipa3_hdr_proc_ctx_offset_entry *offset_entry;
		struct ipa3_hdr_entry *hdr;
		u32 cookie;

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+43 −6

Original line number	Diff line number	Diff line
		@@ -631,7 +631,12 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 29, 14, 8, 8, IPA_EE_AP } },

		/* Dummy consumer (pipe 31) is used in L2TP rt rule */
		[IPA_3_0][IPA_CLIENT_DUMMY_CONS] = {
		true, IPA_v3_0_GROUP_DL, false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 31, 31, 8, 8, IPA_EE_AP } },

		/* IPA_3_5 */
		[IPA_3_5][IPA_CLIENT_WLAN1_PROD] = {
		@@ -778,6 +783,12 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_PCIE,
		{ 19, 13, 8, 8, IPA_EE_AP } },
		/* Dummy consumer (pipe 31) is used in L2TP rt rule */
		[IPA_3_5][IPA_CLIENT_DUMMY_CONS] = {
		true, IPA_v3_5_GROUP_UL_DL, false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_PCIE,
		{ 31, 31, 8, 8, IPA_EE_AP } },

		/* IPA_3_5_MHI */
		[IPA_3_5_MHI][IPA_CLIENT_USB_PROD] = {
		@@ -928,6 +939,12 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_PCIE,
		{ 19, 13, 8, 8, IPA_EE_AP } },
		/* Dummy consumer (pipe 31) is used in L2TP rt rule */
		[IPA_3_5_MHI][IPA_CLIENT_DUMMY_CONS] = {
		true, IPA_v3_5_MHI_GROUP_DMA, false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_PCIE,
		{ 31, 31, 8, 8, IPA_EE_AP } },

		/* IPA_3_5_1 */
		[IPA_3_5_1][IPA_CLIENT_WLAN1_PROD] = {
		@@ -1073,7 +1090,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 11, 2, 4, 6, IPA_EE_AP } },

		/* Dummy consumer (pipe 31) is used in L2TP rt rule */
		[IPA_3_5_1][IPA_CLIENT_DUMMY_CONS] = {
		true, IPA_v3_5_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 31, 31, 8, 8, IPA_EE_AP } },

		/* IPA_4_0 */
		[IPA_4_0][IPA_CLIENT_WLAN1_PROD] = {
		@@ -1273,6 +1296,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_PCIE,
		{ 21, 15, 9, 9, IPA_EE_AP } },
		/* Dummy consumer (pipe 31) is used in L2TP rt rule */
		[IPA_4_0][IPA_CLIENT_DUMMY_CONS] = {
		true, IPA_v4_0_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 31, 31, 8, 8, IPA_EE_AP } },

		/* IPA_4_0_MHI */
		[IPA_4_0_MHI][IPA_CLIENT_USB_PROD] = {
		@@ -1452,8 +1482,13 @@ static const struct ipa_ep_configuration ipa3_ep_mapping
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_PCIE,
		{ 21, 15, 9, 9, IPA_EE_AP } },


		/* Dummy consumer (pipe 31) is used in L2TP rt rule */
		[IPA_4_0_MHI][IPA_CLIENT_DUMMY_CONS] = {
		true, IPA_v4_0_GROUP_UL_DL,
		false,
		IPA_DPS_HPS_SEQ_TYPE_INVALID,
		QMB_MASTER_SELECT_DDR,
		{ 31, 31, 8, 8, IPA_EE_AP } },
		};

		static struct msm_bus_vectors ipa_init_vectors_v3_0[] = {
		@@ -2136,7 +2171,8 @@ int ipa3_get_ep_mapping(enum ipa_client_type client)

		ipa_ep_idx = ipa3_ep_mapping[ipa3_get_hw_type_index()][client].
		ipa_gsi_ep_info.ipa_ep_num;
		if (ipa_ep_idx < 0 \|\| ipa_ep_idx >= IPA3_MAX_NUM_PIPES)
		if (ipa_ep_idx < 0 \|\| (ipa_ep_idx >= IPA3_MAX_NUM_PIPES
		&& client != IPA_CLIENT_DUMMY_CONS))
		return IPA_EP_NOT_ALLOCATED;

		return ipa_ep_idx;
		@@ -2903,7 +2939,8 @@ int ipa3_cfg_ep_mode(u32 clnt_hdl, const struct ipa_ep_cfg_mode *ep_mode)
		if (ep_mode->mode == IPA_DMA)
		type = IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY;
		else
		type = IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP;
		type =
		IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP;

		IPADBG(" set sequencers to sequance 0x%x, ep = %d\n", type,
		clnt_hdl);