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Commit adcdbc66 authored by Jesse Barnes's avatar Jesse Barnes Committed by Eric Anholt
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drm/i915: don't access FW_BLC_SELF on 965G 

The register offset for FW_BLC_SELF is a totally different set of bits
on Broadwater (it's actually MI_RDRET_STATE), so don't treat it like
FW_BLC_SELF on 965G chips.

Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=26874

.

Cc: stable@kernel.org
Tested-by: default avatarNorman Yarvin <yarvin@yarchive.net>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 43ed340a

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -620,7 +620,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	bool sr_enabled = false;



	if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))

	if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev))

		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;

	else if (IS_I915GM(dev))

		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;

drivers/gpu/drm/i915/intel_display.c

+5 −3
Original line number Diff line number Diff line
@@ -2970,9 +2970,11 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, 
		if (srwm < 0)

			srwm = 1;

		srwm &= 0x3f;

		if (IS_I965GM(dev))

			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

	} else {

		/* Turn off self refresh if both pipes are enabled */

		if (IS_I965GM(dev))

			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)

				   & ~FW_BLC_SELF_EN);

	}