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Commit accfad7d authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm: Clear top 16 bits of va only on older cpus 



As per ISA, we need to do this only for architecture version 2.02 and
earlier. This continued to work even for 2.07. But let's not do this for
anything after 2.02. ISA 3.0 requires these top bits to be not cleared.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: default avatarBalbir Singh <bsingharora@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent e21fc93b

arch/powerpc/include/asm/mmu.h

+7 −2
Original line number Diff line number Diff line
@@ -24,6 +24,11 @@ 
/*

 * This is individual features

 */

/*

 * We need to clear top 16bits of va (from the remaining 64 bits )in

 * tlbie* instructions

 */

#define MMU_FTR_TLBIE_CROP_VA		ASM_CONST(0x00008000)



/* Enable use of high BAT registers */

#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)
@@ -97,7 +102,7 @@ 
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\

	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2

#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2

#define MMU_FTRS_PPC970		MMU_FTRS_POWER4

#define MMU_FTRS_PPC970		MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA

#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
@@ -124,7 +129,7 @@ enum { 
		MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |

		MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |

		MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |

		MMU_FTR_1T_SEGMENT |

		MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |

#ifdef CONFIG_PPC_RADIX_MMU

		MMU_FTR_RADIX |

#endif

arch/powerpc/kernel/cputable.c

+2 −2
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER4 (gp)",

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.mmu_features		= MMU_FTRS_POWER4,

		.mmu_features		= MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,
@@ -152,7 +152,7 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.cpu_name		= "POWER4+ (gq)",

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.mmu_features		= MMU_FTRS_POWER4,

		.mmu_features		= MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

arch/powerpc/mm/hash_native_64.c

+4 −2
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) 
	 * Older versions of the architecture (2.02 and earler) require the

	 * masking of the top 16 bits.

	 */

	if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))

		va &= ~(0xffffULL << 48);



	switch (psize) {
@@ -113,6 +114,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) 
	 * Older versions of the architecture (2.02 and earler) require the

	 * masking of the top 16 bits.

	 */

	if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))

		va &= ~(0xffffULL << 48);



	switch (psize) {