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Commit acc6a1a6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/cz/dpm: properly report UVD and VCE clock levels 



VCE, UVD DPM work similarly to SCLK DPM.  Report the current
clock levels for UVD and VCE via debugfs.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2d52cd4

drivers/gpu/drm/amd/amdgpu/cz_dpm.c

+45 −16
Original line number Diff line number Diff line
@@ -505,27 +505,56 @@ static void 
cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,

					       struct seq_file *m)

{

	struct cz_power_info *pi = cz_get_pi(adev);

	struct amdgpu_clock_voltage_dependency_table *table =

		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;

	u32 current_index =

		(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

		TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>

		TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;

	u32 sclk, tmp;

	struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =

		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;

	struct amdgpu_vce_clock_voltage_dependency_table *vce_table =

		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;

	u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),

				       TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);

	u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),

				      TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);

	u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),

				      TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);

	u32 sclk, vclk, dclk, ecclk, tmp;

	u16 vddnb, vddgfx;



	if (current_index >= NUM_SCLK_LEVELS) {

		seq_printf(m, "invalid dpm profile %d\n", current_index);

	if (sclk_index >= NUM_SCLK_LEVELS) {

		seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);

	} else {

		sclk = table->entries[current_index].clk;

		sclk = table->entries[sclk_index].clk;

		seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);

	}



	tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &

	       CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;

	vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);

	tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &

	       CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;

	vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);

		seq_printf(m, "power level %d    sclk: %u vddnb: %u vddgfx: %u\n",

			   current_index, sclk, vddnb, vddgfx);

	seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);



	seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");

	if (!pi->uvd_power_gated) {

		if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {

			seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);

		} else {

			vclk = uvd_table->entries[uvd_index].vclk;

			dclk = uvd_table->entries[uvd_index].dclk;

			seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);

		}

	}



	seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");

	if (!pi->vce_power_gated) {

		if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {

			seq_printf(m, "invalid vce dpm level %d\n", vce_index);

		} else {

			ecclk = vce_table->entries[vce_index].ecclk;

			seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);

		}

	}

}