Merge "ASoC: msm_sdw: Move the delay logic inside bulk write loop" (acbedfa2) · Commits · e / devices / android_kernel_fairphone_FP3

sound/soc/codecs/msm_sdw/msm_sdw_cdc.c

+7 −6

Original line number	Diff line number	Diff line
		@@ -1039,7 +1039,6 @@ static int msm_sdw_swrm_read(void *handle, int reg)
		__func__, reg);
		sdw_rd_addr_base = MSM_SDW_AHB_BRIDGE_RD_ADDR_0;
		sdw_rd_data_base = MSM_SDW_AHB_BRIDGE_RD_DATA_0;

		/*
		* Add sleep as SWR slave access read takes time.
		* Allow for RD_DONE to complete for previous register if any.
		@@ -1054,6 +1053,8 @@ static int msm_sdw_swrm_read(void *handle, int reg)
		dev_err(msm_sdw->dev, "%s: RD Addr Failure\n", __func__);
		goto err;
		}
		/* Add sleep for SWR register read value to get updated. */
		usleep_range(100, 105);
		/* Check for RD value */
		ret = regmap_bulk_read(msm_sdw->regmap, sdw_rd_data_base,
		(u8 *)&val, 4);
		@@ -1079,12 +1080,12 @@ static int msm_sdw_bulk_write(struct msm_sdw_priv *msm_sdw,
		sdw_wr_addr_base = MSM_SDW_AHB_BRIDGE_WR_ADDR_0;
		sdw_wr_data_base = MSM_SDW_AHB_BRIDGE_WR_DATA_0;

		for (i = 0; i < len; i += 2) {
		/*
		* Add sleep as SWR slave write takes time.
		* Allow for any previous pending write to complete.
		*/
		usleep_range(50, 55);
		for (i = 0; i < len; i += 2) {
		usleep_range(100, 105);
		/* First Write the Data to register */
		ret = regmap_bulk_write(msm_sdw->regmap,
		sdw_wr_data_base, bulk_reg[i].buf, 4);