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Commit acbe9157 authored by Gaurav Kohli's avatar Gaurav Kohli
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irqchip: gic-v3: Restore enable bit of spi interrupts 



While setting enable bit of spi interrupt, there is
chance of enabling spurious interrupt which is by default
disabled for soc. So instead of setting restore the
previous state of enable bit.

Change-Id: Ie6e363f04864fc6e36be83ebd20b19b5e6b45f54
Signed-off-by: default avatarGaurav Kohli <gkohli@codeaurora.org>
parent 3d5764bc

drivers/irqchip/irq-gic-v3.c

+2 −2
Original line number Diff line number Diff line
@@ -342,7 +342,7 @@ static void _gic_v3_dist_restore_set_reg(u32 offset) 
}



#define _gic_v3_dist_restore_isenabler()		\

		_gic_v3_dist_restore_set_reg(GICD_ISENABLER)

		_gic_v3_dist_restore_reg(SAVED_IS_ENABLER)



#define _gic_v3_dist_restore_ispending()		\

		_gic_v3_dist_restore_set_reg(GICD_ISPENDR)
@@ -420,7 +420,7 @@ static void _gic_v3_dist_clear_reg(u32 offset) 
 *

 * 5. Set pending for the interrupt.

 *

 * 6. Enable interrupt and wait for its completion.

 * 6. Restore Enable bit of interrupt and wait for its completion.

 *

 */

void gic_v3_dist_restore(void)