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Commit ac67477f authored by Tomeu Vizoso's avatar Tomeu Vizoso Committed by Thierry Reding
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clk: tegra: Set the EMC clock as the parent of the MC clock 



On Tegra124, as we now have a proper driver for the EMC.

Signed-off-by: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 2db04f16

drivers/clk/tegra/clk-tegra124.c

+1 −12
Original line number Diff line number Diff line
@@ -152,11 +152,6 @@ static unsigned long tegra124_input_freq[] = { 
	[12] = 260000000,

};



static const char *mux_pllmcp_clkm[] = {

	"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",

};

#define mux_pllmcp_clkm_idx NULL



static struct div_nmp pllxc_nmp = {

	.divm_shift = 0,

	.divm_width = 8,
@@ -1126,13 +1121,7 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base, 
					     periph_clk_enb_refcnt);

	clks[TEGRA124_CLK_DSIB] = clk;



	/* emc mux */

	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,

			       ARRAY_SIZE(mux_pllmcp_clkm), 0,

			       clk_base + CLK_SOURCE_EMC,

			       29, 3, 0, &emc_lock);



	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,

	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,

				    &emc_lock);

	clks[TEGRA124_CLK_MC] = clk;