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Commit ac5ced91 authored Jun 14, 2012 by Roland Stigge

ARM: LPC32xx: High Speed UART configuration via DT

This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
configuration. On the PHY3250 reference board, UART2 is enabled.

Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>

parent c70426f1

arch/arm/boot/dts/lpc32xx.dtsi

+11 −5

Original line number	Diff line number	Diff line
		@@ -212,18 +212,24 @@
		};

		uart1: serial@40014000 {
		compatible = "nxp,serial";
		compatible = "nxp,lpc3220-hsuart";
		reg = <0x40014000 0x1000>;
		interrupts = <26 0>;
		status = "disabled";
		};

		uart2: serial@40018000 {
		compatible = "nxp,serial";
		compatible = "nxp,lpc3220-hsuart";
		reg = <0x40018000 0x1000>;
		interrupts = <25 0>;
		status = "disabled";
		};

		uart7: serial@4001C000 {
		compatible = "nxp,serial";
		reg = <0x4001C000 0x1000>;
		uart7: serial@4001c000 {
		compatible = "nxp,lpc3220-hsuart";
		reg = <0x4001c000 0x1000>;
		interrupts = <24 0>;
		status = "disabled";
		};

		rtc@40024000 {

arch/arm/boot/dts/phy3250.dts

+4 −0

Original line number	Diff line number	Diff line
		@@ -148,6 +148,10 @@
		};

		fab {
		uart2: serial@40018000 {
		status = "okay";
		};

		tsc@40048000 {
		status = "okay";
		};