Merge "coresight-tpdm: Add support to dump MCMB MSR" (ab5d4673) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/arm/coresight.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -154,6 +154,7 @@ its hardware characteristcs.
		* qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed
		after enabling the subunit.

		* qcom,dump-enable: boolean, specifies to dump MCMB data.
		* Optional properties for CTI:

		* qcom,cti-gpio-trigin: cti trigger input driven by gpio.

+13 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@
		#include <linux/bitmap.h>
		#include <linux/of.h>
		#include <linux/coresight.h>
		#include <soc/qcom/memory_dump.h>

		#include "coresight-priv.h"

		@@ -225,6 +226,7 @@ struct dsb_dataset {
		struct mcmb_dataset {
		uint8_t mcmb_trig_lane;
		uint8_t mcmb_lane_select;
		uint32_t *mcmb_msr_dump_ptr;
		};

		struct cmb_dataset {
		@@ -609,6 +611,11 @@ static void __tpdm_enable_mcmb(struct tpdm_drvdata *drvdata)
		val = val & ~BM(10, 17);
		val = val \| (BMVAL(mcmb->mcmb_lane_select, 0, 7) << 10);

		if (mcmb->mcmb_msr_dump_ptr) {
		for (i = 0; i < TPDM_CMB_MAX_MSR; i++)
		mcmb->mcmb_msr_dump_ptr[i] = drvdata->cmb->msr[i];
		}

		tpdm_writel(drvdata, val, TPDM_CMB_CR);
		/* Set the enable bit */
		val = val \| BIT(0);
		@@ -3910,6 +3917,12 @@ static int tpdm_datasets_alloc(struct tpdm_drvdata *drvdata)
		GFP_KERNEL);
		if (!drvdata->cmb->mcmb)
		return -ENOMEM;

		if (of_property_read_bool(drvdata->dev->of_node,
		"qcom,dump-enable"))
		drvdata->cmb->mcmb->mcmb_msr_dump_ptr =
		(uint32_t *)get_msm_dump_ptr(
		MSM_DUMP_DATA_TPDM_SWAO_MCMB);
		}
		return 0;
		}

+1 −0

Original line number	Diff line number	Diff line
		@@ -86,6 +86,7 @@ enum msm_dump_data_ids {
		MSM_DUMP_DATA_FCM = 0xEE,
		MSM_DUMP_DATA_POWER_REGS = 0xED,
		MSM_DUMP_DATA_TMC_ETF = 0xF0,
		MSM_DUMP_DATA_TPDM_SWAO_MCMB = 0xF2,
		MSM_DUMP_DATA_TMC_REG = 0x100,
		MSM_DUMP_DATA_LOG_BUF = 0x110,
		MSM_DUMP_DATA_LOG_BUF_FIRST_IDX = 0x111,