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Commit aaf24884 authored by Huang Rui's avatar Huang Rui Committed by Ingo Molnar
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perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter 



AMD Zeppelin (Family 17h, Model 00h) introduces an instructions
retired performance counter which is indicated by
CPUID.8000_0008H:EBX[1]. A dedicated Instructions Retired MSR register
(MSR 0xC000_000E9) increments once for every instruction retired.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@suse.de>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Jacob Shin <jacob.w.shin@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <rric@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1454056197-5893-3-git-send-email-ray.huang@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 8a224261

arch/x86/events/msr.c

+19 −11
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ enum perf_msr_id { 
	PERF_MSR_PPERF			= 3,

	PERF_MSR_SMI			= 4,

	PERF_MSR_PTSC			= 5,

	PERF_MSR_IRPERF			= 6,



	PERF_MSR_EVENT_MAX,

};
@@ -21,6 +22,11 @@ static bool test_ptsc(int idx) 
	return boot_cpu_has(X86_FEATURE_PTSC);

}



static bool test_irperf(int idx)

{

	return boot_cpu_has(X86_FEATURE_IRPERF);

}



static bool test_intel(int idx)

{

	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
@@ -81,6 +87,7 @@ PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); 
PMU_EVENT_ATTR_STRING(pperf,  evattr_pperf,  "event=0x03");

PMU_EVENT_ATTR_STRING(smi,    evattr_smi,    "event=0x04");

PMU_EVENT_ATTR_STRING(ptsc,   evattr_ptsc,   "event=0x05");

PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");



static struct perf_msr msr[] = {

	[PERF_MSR_TSC]    = { 0,		&evattr_tsc,	NULL,		 },
@@ -89,6 +96,7 @@ static struct perf_msr msr[] = { 
	[PERF_MSR_PPERF]  = { MSR_PPERF,	&evattr_pperf,	test_intel,	 },

	[PERF_MSR_SMI]    = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },

	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },

	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF,	&evattr_irperf,	test_irperf,	 },

};



static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -251,6 +251,7 @@ 


/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */

#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF	(13*32+1) /* Instructions Retired Count */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */

#define X86_FEATURE_DTHERM	(14*32+ 0) /* Digital Thermal Sensor */

arch/x86/include/asm/msr-index.h

+3 −0
Original line number Diff line number Diff line
@@ -313,6 +313,9 @@ 
#define MSR_AMD64_IBSOPDATA4		0xc001103d

#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */



/* Fam 17h MSRs */

#define MSR_F17H_IRPERF			0xc00000e9



/* Fam 16h MSRs */

#define MSR_F16H_L2I_PERF_CTL		0xc0010230

#define MSR_F16H_L2I_PERF_CTR		0xc0010231