Loading drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c +11 −3 Original line number Original line Diff line number Diff line Loading @@ -3847,7 +3847,7 @@ static int msm_isp_stream_axi_cfg_update(struct vfe_device *vfe_dev, int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) { { int rc = 0, i; int rc = 0, i, j, k; struct msm_vfe_axi_stream *stream_info; struct msm_vfe_axi_stream *stream_info; struct msm_vfe_axi_stream_update_cmd *update_cmd = arg; struct msm_vfe_axi_stream_update_cmd *update_cmd = arg; struct msm_vfe_axi_stream_cfg_update_info *update_info = NULL; struct msm_vfe_axi_stream_cfg_update_info *update_info = NULL; Loading Loading @@ -4126,8 +4126,16 @@ int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) } } vfe_idx = msm_isp_get_vfe_idx_for_stream( vfe_idx = msm_isp_get_vfe_idx_for_stream( vfe_dev, stream_info); vfe_dev, stream_info); msm_isp_stream_axi_cfg_update(vfe_dev, stream_info, for (j = 0; j < stream_info->num_planes; j++) { update_info); stream_info->plane_cfg[vfe_idx][j] = update_info->plane_cfg[j]; for (k = 0; k < stream_info->num_isp; k++) { vfe_dev = stream_info->vfe_dev[k]; vfe_dev->hw_info->vfe_ops.axi_ops. cfg_wm_reg(vfe_dev, stream_info, j); } } } } break; break; } } Loading drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +5 −1 Original line number Original line Diff line number Diff line Loading @@ -410,8 +410,12 @@ static int msm_isp_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev, pr_err("%s: Fetch engine config failed\n", __func__); pr_err("%s: Fetch engine config failed\n", __func__); return -EINVAL; return -EINVAL; } } for (i = 0; i < stream_info->num_planes; i++) for (i = 0; i < stream_info->num_planes; i++) { vfe_dev->hw_info->vfe_ops.axi_ops.enable_wm( vfe_dev->vfe_base, stream_info->wm[vfe_idx][i], 1); wm_reload_mask |= (1 << stream_info->wm[vfe_idx][i]); wm_reload_mask |= (1 << stream_info->wm[vfe_idx][i]); } vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, VFE_SRC_MAX); VFE_SRC_MAX); vfe_dev->hw_info->vfe_ops.axi_ops.reload_wm(vfe_dev, vfe_dev->hw_info->vfe_ops.axi_ops.reload_wm(vfe_dev, Loading Loading
drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c +11 −3 Original line number Original line Diff line number Diff line Loading @@ -3847,7 +3847,7 @@ static int msm_isp_stream_axi_cfg_update(struct vfe_device *vfe_dev, int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) { { int rc = 0, i; int rc = 0, i, j, k; struct msm_vfe_axi_stream *stream_info; struct msm_vfe_axi_stream *stream_info; struct msm_vfe_axi_stream_update_cmd *update_cmd = arg; struct msm_vfe_axi_stream_update_cmd *update_cmd = arg; struct msm_vfe_axi_stream_cfg_update_info *update_info = NULL; struct msm_vfe_axi_stream_cfg_update_info *update_info = NULL; Loading Loading @@ -4126,8 +4126,16 @@ int msm_isp_update_axi_stream(struct vfe_device *vfe_dev, void *arg) } } vfe_idx = msm_isp_get_vfe_idx_for_stream( vfe_idx = msm_isp_get_vfe_idx_for_stream( vfe_dev, stream_info); vfe_dev, stream_info); msm_isp_stream_axi_cfg_update(vfe_dev, stream_info, for (j = 0; j < stream_info->num_planes; j++) { update_info); stream_info->plane_cfg[vfe_idx][j] = update_info->plane_cfg[j]; for (k = 0; k < stream_info->num_isp; k++) { vfe_dev = stream_info->vfe_dev[k]; vfe_dev->hw_info->vfe_ops.axi_ops. cfg_wm_reg(vfe_dev, stream_info, j); } } } } break; break; } } Loading
drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +5 −1 Original line number Original line Diff line number Diff line Loading @@ -410,8 +410,12 @@ static int msm_isp_start_fetch_engine_multi_pass(struct vfe_device *vfe_dev, pr_err("%s: Fetch engine config failed\n", __func__); pr_err("%s: Fetch engine config failed\n", __func__); return -EINVAL; return -EINVAL; } } for (i = 0; i < stream_info->num_planes; i++) for (i = 0; i < stream_info->num_planes; i++) { vfe_dev->hw_info->vfe_ops.axi_ops.enable_wm( vfe_dev->vfe_base, stream_info->wm[vfe_idx][i], 1); wm_reload_mask |= (1 << stream_info->wm[vfe_idx][i]); wm_reload_mask |= (1 << stream_info->wm[vfe_idx][i]); } vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, vfe_dev->hw_info->vfe_ops.core_ops.reg_update(vfe_dev, VFE_SRC_MAX); VFE_SRC_MAX); vfe_dev->hw_info->vfe_ops.axi_ops.reload_wm(vfe_dev, vfe_dev->hw_info->vfe_ops.axi_ops.reload_wm(vfe_dev, Loading