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Commit a98d41d6 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth Committed by Kishon Vijay Abraham I
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phy: berlin-sata: Move PHY_BASE into private data struct 



Currently, Berlin SATA PHY driver assumes PHY_BASE address being
constant. While this PHY_BASE is correct for BG2Q, older BG2 PHY_BASE
is different. Prepare the driver for BG2 support by moving the phy_base
into private driver data.

Acked-by: default avatarAntoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 6827a46f

drivers/phy/phy-berlin-sata.c

+15 −9
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
#define MBUS_WRITE_REQUEST_SIZE_128	(BIT(2) << 16)

#define MBUS_READ_REQUEST_SIZE_128	(BIT(2) << 19)



#define PHY_BASE		0x200

#define BG2Q_PHY_BASE		0x200



/* register 0x01 */

#define REF_FREF_SEL_25		BIT(0)
@@ -61,15 +61,16 @@ struct phy_berlin_priv { 
	struct clk		*clk;

	struct phy_berlin_desc	**phys;

	unsigned		nphys;

	u32			phy_base;

};



static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 reg,

					       u32 mask, u32 val)

static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,

			       u32 phy_base, u32 reg, u32 mask, u32 val)

{

	u32 regval;



	/* select register */

	writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR);

	writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);



	/* set bits */

	regval = readl(ctrl_reg + PORT_VSR_DATA);
@@ -103,17 +104,20 @@ static int phy_berlin_sata_power_on(struct phy *phy) 
	writel(regval, priv->base + HOST_VSA_DATA);



	/* set PHY mode and ref freq to 25 MHz */

	phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff,

				    REF_FREF_SEL_25 | PHY_MODE_SATA);

	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,

				    0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);



	/* set PHY up to 6 Gbps */

	phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0);

	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,

				    0x0c00, PHY_GEN_MAX_6_0);



	/* set 40 bits width */

	phy_berlin_sata_reg_setbits(ctrl_reg, 0x23,  0xc00, DATA_BIT_WIDTH_40);

	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,

				    0x0c00, DATA_BIT_WIDTH_40);



	/* use max pll rate */

	phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE);

	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,

				    0x0000, USE_MAX_PLL_RATE);



	/* set Gen3 controller speed */

	regval = readl(ctrl_reg + PORT_SCR_CTL);
@@ -218,6 +222,8 @@ static int phy_berlin_sata_probe(struct platform_device *pdev) 
	if (!priv->phys)

		return -ENOMEM;



	priv->phy_base = BG2Q_PHY_BASE;



	dev_set_drvdata(dev, priv);

	spin_lock_init(&priv->lock);