Merge "ARM: dts: msm: Add GPU DTSI entries for SDM845v2"

	sw-reset = <&gpu_gx_sw_reset>;

	qcom,reset-aon-logic;

};

/* GPU overrides */

&msm_gpu {

	/* Updated chip ID */

	qcom,chipid = <0x06030001>;

	qcom,initial-pwrlevel = <5>;

	qcom,gpu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevels";

		qcom,gpu-pwrlevel@0 {

			reg = <0>;

			qcom,gpu-freq = <675000000>;

			qcom,bus-freq = <12>;

			qcom,bus-min = <10>;

			qcom,bus-max = <12>;

		};

		qcom,gpu-pwrlevel@1 {

			reg = <1>;

			qcom,gpu-freq = <596000000>;

			qcom,bus-freq = <10>;

			qcom,bus-min = <9>;

			qcom,bus-max = <11>;

		};

		qcom,gpu-pwrlevel@2 {

			reg = <2>;

			qcom,gpu-freq = <520000000>;

			qcom,bus-freq = <9>;

			qcom,bus-min = <8>;

			qcom,bus-max = <10>;

		};

		qcom,gpu-pwrlevel@3 {

			reg = <3>;

			qcom,gpu-freq = <414000000>;

			qcom,bus-freq = <8>;

			qcom,bus-min = <7>;

			qcom,bus-max = <9>;

		};

		qcom,gpu-pwrlevel@4 {

			reg = <4>;

			qcom,gpu-freq = <342000000>;

			qcom,bus-freq = <6>;

			qcom,bus-min = <5>;

			qcom,bus-max = <7>;

		};

		qcom,gpu-pwrlevel@5 {

			reg = <5>;

			qcom,gpu-freq = <257000000>;

			qcom,bus-freq = <4>;

			qcom,bus-min = <3>;

			qcom,bus-max = <5>;

		};

		qcom,gpu-pwrlevel@6 {

			reg = <6>;

			qcom,gpu-freq = <0>;

			qcom,bus-freq = <0>;

			qcom,bus-min = <0>;

			qcom,bus-max = <0>;

		};

	};

};

&gmu {

	qcom,gmu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,gmu-pwrlevels";

		qcom,gmu-pwrlevel@0 {

			reg = <0>;

			qcom,gmu-freq = <500000000>;

		};

		qcom,gmu-pwrlevel@1 {

			reg = <1>;

			qcom,gmu-freq = <200000000>;

		};

		qcom,gmu-pwrlevel@2 {

			reg = <2>;

			qcom,gmu-freq = <0>;

		};

	};

};