Merge "msm: vidc: Introduce device specific code for video driver"

Required properties:

- compatible : one of:

	- "qcom,msm-vidc"

- qcom,max-hw-load: The maximum load the hardware can support expressed in units

  of macroblocks per second. The load is a reflection of hardware capability

  rather than a performance guarantee. Performance is guaranteed only up to

  advertised capability of the chipset.

- qcom,max-hq-mbs-per-frame : Max no of mbs per frame beyond which

    "High Quality" encoding is not supported.

- qcom,max-hq-frames-per-sec : Max no of frames per second beyond which

    "High Quality" encoding is not supported.

        - "qcom,sdm845-vidc" : Invokes driver specific data for SDM845.

Optional properties:

- reg : offset and length of the register set for the device.

- interrupts : should contain the vidc interrupt.

- qcom,platform-version : mask and shift of the platform version bits

    in efuse register.

- qcom,reg-presets : list of offset-value pairs for registers to be written.

  The offsets are from the base offset specified in 'reg'. This is mainly

  used for QoS, VBIF, etc. presets for video.

       macro block in low power mode.

       the required frequency to get the final frequency, the factor is

       represented in Q16 format.

- qcom,sw-power-collapse = A bool indicating if video hardware core can be

  power collapsed in idle state.

- qcom,never-unload-fw = A bool indicating if video firmware should be not be

  unloaded after all active sessions have closed.  Once a new session starts up

  after this, the firmware will be ready to go.  This should be set on platforms

  that desire low-latency video startup and don't mind "leakage" of some memory.

- qcom,use-non-secure-pil = A bool indicating which type of pil to use to load

  the fw.

- qcom,fw-bias = The address at which venus fw is loaded (manually).

- qcom,enable-thermal-mitigation = A bool to enable thermal mitigation when

  thermal run away occurs.

- qcom,hfi-version = The hfi packetization version supported by venus firmware.

  If hfi version is not specified, then packetization type will default to

  legacy.

- qcom,vidc-iommu-domains = node containing individual domain nodes, each with:

     - a unique domain name for the domain node (e.g vidc,domain-ns)

     - qcom,vidc-domain-phandle: phandle for the domain as defined in

           internal persist = 0x200

           internal persist1 = 0x400

           internal cmd queue = 0x800

- qcom,pm-qos-latency-us = The latency used to vote for QOS power manager. This

value is typically max(latencies of every cluster at all power levels) + 1

- qcom,max-secure-instances = An int containing max number of concurrent secure

  instances supported, accounting for venus and system wide limitations like

  memory, performance etc.

- qcom,debug-timeout = A bool indicating that FW errors such as SYS_ERROR,

  SESSION_ERROR and timeouts will be treated as Fatal.

- cache-slice-names = An array of supported cache slice names by llcc

- cache-slices = An array of supported cache slice ids corresponding

  to cache-slice-names by llcc

		venus-supply = <&gdsc>;

		venus-core0-supply = <&gdsc1>;

		venus-core1-supply = <&gdsc2>;

		qcom,hfi-version = "3xx";

		qcom,reg-presets = <0x80004 0x1>,

			<0x80178 0x00001FFF>;

		qcom,qdss-presets = <0xFC307000 0x1000>,

			<0xFC322000 0x1000>;

		qcom,max-hw-load = <1224450>; /* 4k @ 30 + 1080p @ 30*/

		qcom,never-unload-fw;

		clock-names = "foo_clk", "bar_clk", "baz_clk";

		qcom,clock-configs = <0x3 0x1 0x0>;

		qcom,sw-power-collapse;

		qcom,buffer-type-tz-usage-table = <0x1 0x1>,

						<0x1fe 0x2>;

		qcom,enable-thermal-mitigation;

		qcom,use-non-secure-pil;

		qcom,use_dynamic_bw_update;

		qcom,fw-bias = <0xe000000>;

		qcom,allowed-clock-rates = <200000000 300000000 400000000>;

		qcom,max-hq-mbs-per-frame = <8160>;

		qcom,max-hq-frames-per-sec = <60>;

		msm_vidc_cb1: msm_vidc_cb1 {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";

&soc {

	msm_vidc: qcom,vidc@aa00000 {

		compatible = "qcom,msm-vidc";

		compatible = "qcom,msm-vidc", "qcom,sdm845-vidc";

		status = "ok";

		reg = <0xaa00000 0x200000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

		qcom,hfi = "venus";

		qcom,firmware-name = "venus";

		qcom,never-unload-fw;

		qcom,sw-power-collapse;

		qcom,max-secure-instances = <5>;

		qcom,max-hw-load = <2563200>; /* Full 4k @ 60 + 1080p @ 60 */

		/* LLCC Info */

		cache-slice-names = "vidsc0", "vidsc1";

		qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x1 0x0>;

		qcom,allowed-clock-rates = <200000000 320000000 380000000

			444000000 533000000>;

		qcom,max-hq-mbs-per-frame = <8160>;

		qcom,max-hq-frames-per-sec = <60>;

		qcom,clock-freq-tbl {

			qcom,profile-enc {

				qcom,codec-mask = <0x55555555>;

				qcom,vpp-cycles-per-mb = <675>;

				qcom,vsp-cycles-per-mb = <125>;

				qcom,low-power-cycles-per-mb = <320>;

			};

			qcom,profile-dec {

				qcom,codec-mask = <0xffffffff>;

				qcom,vpp-cycles-per-mb = <200>;

				qcom,vsp-cycles-per-mb = <50>;

			};

		};

		/* Buses */

		bus_cnoc {

ccflags-y += -I$(srctree)/drivers/media/platform/msm/vidc/

msm-vidc-objs := msm_v4l2_vidc.o \

				msm_vidc_platform.o \

                                msm_vidc_common.o \

                                msm_vidc.o \

                                msm_vdec.o \

struct msm_vidc_drv *vidc_driver;

uint32_t msm_vidc_pwr_collapse_delay = 3000;

static inline struct msm_vidc_inst *get_vidc_inst(struct file *filp, void *fh)

{

	core->resources.pdev = pdev;

	if (pdev->dev.of_node) {

		/* Target supports DT, parse from it */

		rc = read_platform_resources_from_drv_data(core);

		rc = read_platform_resources_from_dt(&core->resources);

	} else {

		dprintk(VIDC_ERR, "pdev node is NULL\n");

{

	unsigned long val = 0;

	int rc = 0;

	struct msm_vidc_core *core = NULL;

	rc = kstrtoul(buf, 0, &val);

	if (rc)

		return rc;

	else if (!val)

		return -EINVAL;

	msm_vidc_pwr_collapse_delay = val;

	core = get_vidc_core(MSM_VIDC_CORE_VENUS);

	if (!core)

		return -EINVAL;

	core->resources.msm_vidc_pwr_collapse_delay = val;

	return count;

}

		struct device_attribute *attr,

		char *buf)

{

	return snprintf(buf, PAGE_SIZE, "%u\n", msm_vidc_pwr_collapse_delay);

	struct msm_vidc_core *core = NULL;

	core = get_vidc_core(MSM_VIDC_CORE_VENUS);

	if (!core)

		return -EINVAL;

	return snprintf(buf, PAGE_SIZE, "%u\n",

		core->resources.msm_vidc_pwr_collapse_delay);

}

static DEVICE_ATTR(pwr_collapse_delay, 0644, show_pwr_collapse_delay,

		goto err_no_mem;

	}

	core->platform_data = vidc_get_drv_data(&pdev->dev);

	dev_set_drvdata(&pdev->dev, core);

	rc = msm_vidc_initialize_core(pdev, core);

	if (rc) {

	return true;

}

static bool msm_dcvs_check_codec_supported(int fourcc,

		unsigned long codecs_supported, enum session_type type)

{

	int codec_bit, session_type_bit;

	bool codec_type, session_type;

	unsigned long session;

	session = VIDC_VOTE_DATA_SESSION_VAL(get_hal_codec(fourcc),

		get_hal_domain(type));

	if (!codecs_supported || !session)

		return false;

	/* ffs returns a 1 indexed, test_bit takes a 0 indexed...index */

	codec_bit = ffs(session) - 1;

	session_type_bit = codec_bit + 1;

	codec_type =

		test_bit(codec_bit, &codecs_supported) ==

		test_bit(codec_bit, &session);

	session_type =

		test_bit(session_type_bit, &codecs_supported) ==

		test_bit(session_type_bit, &session);

	return codec_type && session_type;

}

int msm_comm_init_clocks_and_bus_data(struct msm_vidc_inst *inst)

{

	int rc = 0, j = 0;

	struct clock_freq_table *clk_freq_tbl = NULL;

	struct clock_profile_entry *entry = NULL;

	int fourcc;

	int fourcc, count;

	if (!inst || !inst->core) {

		dprintk(VIDC_ERR, "%s Invalid args: Inst = %pK\n",

				__func__, inst);

		return -EINVAL;

	}

	clk_freq_tbl = &inst->core->resources.clock_freq_tbl;

	count = inst->core->resources.codec_data_count;

	fourcc = inst->session_type == MSM_VIDC_DECODER ?

		inst->fmts[OUTPUT_PORT].fourcc :

		inst->fmts[CAPTURE_PORT].fourcc;

	for (j = 0; j < clk_freq_tbl->count; j++) {

		bool matched = false;

		entry = &clk_freq_tbl->clk_prof_entries[j];

		matched = msm_dcvs_check_codec_supported(

				fourcc,

				entry->codec_mask,

				inst->session_type);

		if (matched) {

			inst->clk_data.entry = entry;

	for (j = 0; j < count; j++) {

		if (inst->core->resources.codec_data[j].session_type ==

				inst->session_type &&

				inst->core->resources.codec_data[j].fourcc ==

				fourcc) {

			inst->clk_data.entry =

				&inst->core->resources.codec_data[j];

			break;

		}

	}

	if (j == clk_freq_tbl->count) {

		dprintk(VIDC_ERR,

			"Failed : No matching clock entry found\n");

		rc = -EINVAL;

	}

	return rc;

}