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Commit a8749af1 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv20/fb: split implementation into nv20/nv25 pieces 



There's more stuff that can be shared in the constructor, will be merged
together again later.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 67e9e9f6

drivers/gpu/drm/nouveau/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ nouveau-y += core/subdev/fb/base.o 
nouveau-y += core/subdev/fb/nv04.o

nouveau-y += core/subdev/fb/nv10.o

nouveau-y += core/subdev/fb/nv20.o

nouveau-y += core/subdev/fb/nv25.o

nouveau-y += core/subdev/fb/nv30.o

nouveau-y += core/subdev/fb/nv40.o

nouveau-y += core/subdev/fb/nv50.o

drivers/gpu/drm/nouveau/core/include/subdev/fb.h

+6 −0
Original line number Diff line number Diff line
@@ -114,6 +114,7 @@ int _nouveau_fb_init(struct nouveau_object *); 
extern struct nouveau_oclass nv04_fb_oclass;

extern struct nouveau_oclass nv10_fb_oclass;

extern struct nouveau_oclass nv20_fb_oclass;

extern struct nouveau_oclass nv25_fb_oclass;

extern struct nouveau_oclass nv30_fb_oclass;

extern struct nouveau_oclass nv40_fb_oclass;

extern struct nouveau_oclass nv50_fb_oclass;
@@ -126,6 +127,11 @@ bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype); 


void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);



void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,

		       u32 pitch, u32 flags, struct nouveau_fb_tile *);

void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);

void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);



void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,

		       u32 pitch, u32 flags, struct nouveau_fb_tile *);

void nv30_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);

drivers/gpu/drm/nouveau/core/subdev/device/nv20.c

+3 −3
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ nv20_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv25_fb_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -90,7 +90,7 @@ nv20_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv25_fb_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@@ -108,7 +108,7 @@ nv20_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv20_fb_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] = &nv25_fb_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;

drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c

+6 −14
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ struct nv20_fb_priv { 
	struct nouveau_fb base;

};



static void

void

nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,

		  u32 flags, struct nouveau_fb_tile *tile)

{
@@ -47,7 +47,6 @@ static void 
nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,

		  struct nouveau_fb_tile *tile)

{

	struct nouveau_device *device = nv_device(pfb);

	int bpp = (flags & 2) ? 32 : 16;



	/* Allocate some of the on-die tag memory, used to store Z
@@ -59,20 +58,13 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, 
	if (!nouveau_mm_head(&pfb->tags, 1, size, size, 1, &tile->tag)) {

		/* Enable Z compression */

		tile->zcomp = tile->tag->offset;

		if (device->chipset >= 0x25) {

			if (bpp == 16)

				tile->zcomp |= 0x00100000;

			else

				tile->zcomp |= 0x00200000;

		} else {

		tile->zcomp |= 0x80000000;

		if (bpp != 16)

			tile->zcomp |= 0x04000000;

	}

}

}



static void

void

nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)

{

	tile->addr  = 0;
@@ -82,7 +74,7 @@ nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) 
	nouveau_mm_free(&pfb->tags, &tile->tag);

}



static void

void

nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)

{

	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);

drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c

0 → 100644
+104 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2010 Francisco Jerez.

 * All Rights Reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining

 * a copy of this software and associated documentation files (the

 * "Software"), to deal in the Software without restriction, including

 * without limitation the rights to use, copy, modify, merge, publish,

 * distribute, sublicense, and/or sell copies of the Software, and to

 * permit persons to whom the Software is furnished to do so, subject to

 * the following conditions:

 *

 * The above copyright notice and this permission notice (including the

 * next paragraph) shall be included in all copies or substantial

 * portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE

 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION

 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION

 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include <subdev/fb.h>



struct nv25_fb_priv {

	struct nouveau_fb base;

};



static void

nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,

		  struct nouveau_fb_tile *tile)

{

	int bpp = (flags & 2) ? 32 : 16;



	/* Allocate some of the on-die tag memory, used to store Z

	 * compression meta-data (most likely just a bitmap determining

	 * if a given tile is compressed or not).

	 */

	size /= 256;



	if (!nouveau_mm_head(&pfb->tags, 1, size, size, 1, &tile->tag)) {

		/* Enable Z compression */

		tile->zcomp = tile->tag->offset;

		if (bpp == 16)

			tile->zcomp |= 0x00100000;

		else

			tile->zcomp |= 0x00200000;

	}

}



static int

nv25_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	     struct nouveau_oclass *oclass, void *data, u32 size,

	     struct nouveau_object **pobject)

{

	struct nouveau_device *device = nv_device(parent);

	struct nv25_fb_priv *priv;

	u32 pbus1218;

	int ret;



	ret = nouveau_fb_create(parent, engine, oclass, &priv);

	*pobject = nv_object(priv);

	if (ret)

		return ret;



	pbus1218 = nv_rd32(priv, 0x001218);

	switch (pbus1218 & 0x00000300) {

	case 0x00000000: priv->base.ram.type = NV_MEM_TYPE_SDRAM; break;

	case 0x00000100: priv->base.ram.type = NV_MEM_TYPE_DDR1; break;

	case 0x00000200: priv->base.ram.type = NV_MEM_TYPE_GDDR3; break;

	case 0x00000300: priv->base.ram.type = NV_MEM_TYPE_GDDR2; break;

	}

	priv->base.ram.size = nv_rd32(priv, 0x10020c) & 0xff000000;



	if (device->chipset >= 0x25)

		ret = nouveau_mm_init(&priv->base.tags, 0, 64 * 1024, 1);

	else

		ret = nouveau_mm_init(&priv->base.tags, 0, 32 * 1024, 1);

	if (ret)

		return ret;



	priv->base.memtype_valid = nv04_fb_memtype_valid;

	priv->base.tile.regions = 8;

	priv->base.tile.init = nv20_fb_tile_init;

	priv->base.tile.comp = nv25_fb_tile_comp;

	priv->base.tile.fini = nv20_fb_tile_fini;

	priv->base.tile.prog = nv20_fb_tile_prog;

	return nouveau_fb_created(&priv->base);

}



struct nouveau_oclass

nv25_fb_oclass = {

	.handle = NV_SUBDEV(FB, 0x25),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv25_fb_ctor,

		.dtor = _nouveau_fb_dtor,

		.init = _nouveau_fb_init,

		.fini = _nouveau_fb_fini,

	},

};