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Commit a8300e07 authored by Lokesh Batra's avatar Lokesh Batra
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msm: kgsl: Add coresight support for Adreno 630 



Add GPU debugbus and coresight register definitions and debugfs access
for Adreno 630.

CRs-Fixed: 2143472
Change-Id: I46d68564dc32541a4bfa473523e022bb2ee22176
Signed-off-by: default avatarLokesh Batra <lbatra@codeaurora.org>
parent 51115737

drivers/gpu/msm/a6xx_reg.h

+70 −2
Original line number Diff line number Diff line
@@ -533,6 +533,8 @@ 
#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT_SHIFT       0x1C

#define A6XX_DBGC_CFG_DBGBUS_CNTLM                  0x605

#define A6XX_DBGC_CFG_DBGBUS_CTLTM_ENABLE_SHIFT     0x18

#define A6XX_DBGC_CFG_DBGBUS_OPL                    0x606

#define A6XX_DBGC_CFG_DBGBUS_OPE                    0x607

#define A6XX_DBGC_CFG_DBGBUS_IVTL_0                 0x608

#define A6XX_DBGC_CFG_DBGBUS_IVTL_1                 0x609

#define A6XX_DBGC_CFG_DBGBUS_IVTL_2                 0x60a
@@ -559,8 +561,40 @@ 
#define A6XX_DBGC_CFG_DBGBUS_BYTEL13_SHIFT          0x14

#define A6XX_DBGC_CFG_DBGBUS_BYTEL14_SHIFT          0x18

#define A6XX_DBGC_CFG_DBGBUS_BYTEL15_SHIFT          0x1C

#define A6XX_DBGC_CFG_DBGBUS_IVTE_0                 0x612

#define A6XX_DBGC_CFG_DBGBUS_IVTE_1                 0x613

#define A6XX_DBGC_CFG_DBGBUS_IVTE_2                 0x614

#define A6XX_DBGC_CFG_DBGBUS_IVTE_3                 0x615

#define A6XX_DBGC_CFG_DBGBUS_MASKE_0                0x616

#define A6XX_DBGC_CFG_DBGBUS_MASKE_1                0x617

#define A6XX_DBGC_CFG_DBGBUS_MASKE_2                0x618

#define A6XX_DBGC_CFG_DBGBUS_MASKE_3                0x619

#define A6XX_DBGC_CFG_DBGBUS_NIBBLEE                0x61a

#define A6XX_DBGC_CFG_DBGBUS_PTRC0                  0x61b

#define A6XX_DBGC_CFG_DBGBUS_PTRC1                  0x61c

#define A6XX_DBGC_CFG_DBGBUS_LOADREG                0x61d

#define A6XX_DBGC_CFG_DBGBUS_IDX                    0x61e

#define A6XX_DBGC_CFG_DBGBUS_CLRC                   0x61f

#define A6XX_DBGC_CFG_DBGBUS_LOADIVT                0x620

#define A6XX_DBGC_VBIF_DBG_CNTL                     0x621

#define A6XX_DBGC_DBG_LO_HI_GPIO                    0x622

#define A6XX_DBGC_EXT_TRACE_BUS_CNTL                0x623

#define A6XX_DBGC_READ_AHB_THROUGH_DBG              0x624

#define A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1             0x62f

#define A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2             0x630

#define A6XX_DBGC_EVT_CFG                           0x640

#define A6XX_DBGC_EVT_INTF_SEL_0                    0x641

#define A6XX_DBGC_EVT_INTF_SEL_1                    0x642

#define A6XX_DBGC_PERF_ATB_CFG                      0x643

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_0            0x644

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_1            0x645

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_2            0x646

#define A6XX_DBGC_PERF_ATB_COUNTER_SEL_3            0x647

#define A6XX_DBGC_PERF_ATB_TRIG_INTF_SEL_0          0x648

#define A6XX_DBGC_PERF_ATB_TRIG_INTF_SEL_1          0x649

#define A6XX_DBGC_PERF_ATB_DRAIN_CMD                0x64a

#define A6XX_DBGC_ECO_CNTL                          0x650

#define A6XX_DBGC_AHB_DBG_CNTL                      0x651



/* VSC registers */

#define A6XX_VSC_PERFCTR_VSC_SEL_0          0xCD8
@@ -800,12 +834,16 @@ 
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_B                   0x18401

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_C                   0x18402

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D                   0x18403

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_INDEX_SHIFT    0x0

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT  0x8

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT                   0x18404

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN_SHIFT     0x0

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU_SHIFT       0xC

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT_SHIFT        0x1C

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM                   0x18405

#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE_SHIFT      0x18

#define A6XX_CX_DBGC_CFG_DBGBUS_OPL                     0x18406

#define A6XX_CX_DBGC_CFG_DBGBUS_OPE                     0x18407

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0                  0x18408

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1                  0x18409

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2                  0x1840A
@@ -832,10 +870,40 @@ 
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL13_SHIFT           0x14

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL14_SHIFT           0x18

#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL15_SHIFT           0x1C

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_0                  0x18412

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_1                  0x18413

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_2                  0x18414

#define A6XX_CX_DBGC_CFG_DBGBUS_IVTE_3                  0x18415

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_0                 0x18416

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_1                 0x18417

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_2                 0x18418

#define A6XX_CX_DBGC_CFG_DBGBUS_MASKE_3                 0x18419

#define A6XX_CX_DBGC_CFG_DBGBUS_NIBBLEE                 0x1841A

#define A6XX_CX_DBGC_CFG_DBGBUS_PTRC0                   0x1841B

#define A6XX_CX_DBGC_CFG_DBGBUS_PTRC1                   0x1841C

#define A6XX_CX_DBGC_CFG_DBGBUS_LOADREG                 0x1841D

#define A6XX_CX_DBGC_CFG_DBGBUS_IDX                     0x1841E

#define A6XX_CX_DBGC_CFG_DBGBUS_CLRC                    0x1841F

#define A6XX_CX_DBGC_CFG_DBGBUS_LOADIVT                 0x18420

#define A6XX_CX_DBGC_VBIF_DBG_CNTL                      0x18421

#define A6XX_CX_DBGC_DBG_LO_HI_GPIO                     0x18422

#define A6XX_CX_DBGC_EXT_TRACE_BUS_CNTL                 0x18423

#define A6XX_CX_DBGC_READ_AHB_THROUGH_DBG               0x18424

#define A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1              0x1842F

#define A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2              0x18430

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_INDEX_SHIFT    0x0

#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT  0x8

#define A6XX_CX_DBGC_EVT_CFG                            0x18440

#define A6XX_CX_DBGC_EVT_INTF_SEL_0                     0x18441

#define A6XX_CX_DBGC_EVT_INTF_SEL_1                     0x18442

#define A6XX_CX_DBGC_PERF_ATB_CFG                       0x18443

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_0             0x18444

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_1             0x18445

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_2             0x18446

#define A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_3             0x18447

#define A6XX_CX_DBGC_PERF_ATB_TRIG_INTF_SEL_0           0x18448

#define A6XX_CX_DBGC_PERF_ATB_TRIG_INTF_SEL_1           0x18449

#define A6XX_CX_DBGC_PERF_ATB_DRAIN_CMD                 0x1844A

#define A6XX_CX_DBGC_ECO_CNTL                           0x18450

#define A6XX_CX_DBGC_AHB_DBG_CNTL                       0x18451



/* GMU control registers */

#define A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL   0x1A880

drivers/gpu/msm/adreno.h

+10 −2
Original line number Diff line number Diff line
@@ -377,6 +377,13 @@ struct adreno_gpu_core { 
	unsigned int max_power;

};





enum gpu_coresight_sources {

	GPU_CORESIGHT_GX = 0,

	GPU_CORESIGHT_CX = 1,

	GPU_CORESIGHT_MAX,

};



/**

 * struct adreno_device - The mothership structure for all adreno related info

 * @dev: Reference to struct kgsl_device
@@ -511,7 +518,7 @@ struct adreno_device { 
	unsigned int speed_bin;

	unsigned int quirks;



	struct coresight_device *csdev;

	struct coresight_device *csdev[GPU_CORESIGHT_MAX];

	uint32_t gpmu_throttle_counters[ADRENO_GPMU_THROTTLE_COUNTERS];

	struct work_struct irq_storm_work;
@@ -565,6 +572,7 @@ enum adreno_device_flags { 
	ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED = 13,

	ADRENO_DEVICE_HARD_RESET = 14,

	ADRENO_DEVICE_PREEMPTION_EXECUTION = 15,

	ADRENO_DEVICE_CORESIGHT_CX = 16,

};



/**
@@ -878,7 +886,7 @@ struct adreno_gpudev { 
	const struct adreno_invalid_countables *invalid_countables;

	struct adreno_snapshot_data *snapshot_data;



	struct adreno_coresight *coresight;

	struct adreno_coresight *coresight[GPU_CORESIGHT_MAX];



	struct adreno_irq *irq;

	int num_prio_levels;

drivers/gpu/msm/adreno_a3xx.c

+1 −1
Original line number Diff line number Diff line
@@ -1923,5 +1923,5 @@ struct adreno_gpudev adreno_a3xx_gpudev = { 
	.perfcounter_close = a3xx_perfcounter_close,

	.start = a3xx_start,

	.snapshot = a3xx_snapshot,

	.coresight = &a3xx_coresight,

	.coresight = {&a3xx_coresight},

};

drivers/gpu/msm/adreno_a4xx.c

+1 −1
Original line number Diff line number Diff line
@@ -1790,7 +1790,7 @@ struct adreno_gpudev adreno_a4xx_gpudev = { 
	.rb_start = a4xx_rb_start,

	.init = a4xx_init,

	.microcode_read = a3xx_microcode_read,

	.coresight = &a4xx_coresight,

	.coresight = {&a4xx_coresight},

	.start = a4xx_start,

	.snapshot = a4xx_snapshot,

	.is_sptp_idle = a4xx_is_sptp_idle,

drivers/gpu/msm/adreno_a5xx.c

+1 −1
Original line number Diff line number Diff line
@@ -3597,7 +3597,7 @@ struct adreno_gpudev adreno_a5xx_gpudev = { 
	.int_bits = a5xx_int_bits,

	.ft_perf_counters = a5xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a5xx_ft_perf_counters),

	.coresight = &a5xx_coresight,

	.coresight = {&a5xx_coresight},

	.start = a5xx_start,

	.snapshot = a5xx_snapshot,

	.irq = &a5xx_irq,