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Commit a816d250 authored by Ulf Hansson's avatar Ulf Hansson Committed by Mike Turquette
Browse files

clk: ux500: Support for prcmu_scalable_rate clock 



The prcmu_scalable_rate clock can change rate but is not gateable.

Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent b2302c87

drivers/clk/ux500/clk-prcmu.c

+17 −0
Original line number Diff line number Diff line
@@ -187,6 +187,13 @@ static struct clk_ops clk_prcmu_gate_ops = { 
	.recalc_rate = clk_prcmu_recalc_rate,

};



static struct clk_ops clk_prcmu_scalable_rate_ops = {

	.is_enabled = clk_prcmu_is_enabled,

	.recalc_rate = clk_prcmu_recalc_rate,

	.round_rate = clk_prcmu_round_rate,

	.set_rate = clk_prcmu_set_rate,

};



static struct clk_ops clk_prcmu_rate_ops = {

	.is_enabled = clk_prcmu_is_enabled,

	.recalc_rate = clk_prcmu_recalc_rate,
@@ -278,6 +285,16 @@ struct clk *clk_reg_prcmu_gate(const char *name, 
			&clk_prcmu_gate_ops);

}



struct clk *clk_reg_prcmu_scalable_rate(const char *name,

					const char *parent_name,

					u8 cg_sel,

					unsigned long rate,

					unsigned long flags)

{

	return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,

			&clk_prcmu_scalable_rate_ops);

}



struct clk *clk_reg_prcmu_rate(const char *name,

			       const char *parent_name,

			       u8 cg_sel,

drivers/clk/ux500/clk.h

+6 −0
Original line number Diff line number Diff line
@@ -35,6 +35,12 @@ struct clk *clk_reg_prcmu_gate(const char *name, 
			       u8 cg_sel,

			       unsigned long flags);



struct clk *clk_reg_prcmu_scalable_rate(const char *name,

					const char *parent_name,

					u8 cg_sel,

					unsigned long rate,

					unsigned long flags);



struct clk *clk_reg_prcmu_rate(const char *name,

			       const char *parent_name,

			       u8 cg_sel,