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Commit a81349a7 authored Oct 27, 2014 by Alexandre Courbot Committed by Ben Skeggs Dec 02, 2014

drm/nouveau: allocate GPFIFOs and fences coherently



Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to
allow them to be safely accessed by the kernel without being synced
on non-coherent architectures.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

parent c3a0c771

drivers/gpu/drm/nouveau/nouveau_chan.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -102,7 +102,7 @@ nouveau_channel_prep(struct nouveau_drm drm, struct nvif_device device,
		chan->drm = drm;

		/* allocate memory for dma push buffer */
		target = TTM_PL_FLAG_TT;
		target = TTM_PL_FLAG_TT \| TTM_PL_FLAG_UNCACHED;
		if (nouveau_vram_pushbuf)
		target = TTM_PL_FLAG_VRAM;

drivers/gpu/drm/nouveau/nv84_fence.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -246,8 +246,8 @@ nv84_fence_create(struct nouveau_drm *drm)

		if (ret == 0)
		ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
		TTM_PL_FLAG_TT, 0, 0, NULL, NULL,
		&priv->bo_gart);
		TTM_PL_FLAG_TT \| TTM_PL_FLAG_UNCACHED, 0,
		0, NULL, NULL, &priv->bo_gart);
		if (ret == 0) {
		ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT);
		if (ret == 0) {