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Commit a7ef94e6 authored by H. Peter Anvin's avatar H. Peter Anvin Committed by Ingo Molnar
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x86: do not promote TM3x00/TM5x00 to i686-class 



We have been promoting Transmeta TM3x00/TM5x00 chips to i686-class
based on the notion that they contain all the user-space visible
features of an i686-class chip.  However, this is not actually true:
they lack the EA-taking long NOPs (0F 1F /0).  Since this is a
userspace-visible incompatibility, downgrade these CPUs to the
manufacturer-defined i586 level.

Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent b02a7f22

arch/x86/kernel/cpu/transmeta.c

+0 −7
Original line number Diff line number Diff line
@@ -76,13 +76,6 @@ static void __cpuinit init_transmeta(struct cpuinfo_x86 *c) 
	/* All Transmeta CPUs have a constant TSC */

	set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);

	

	/* If we can run i686 user-space code, call us an i686 */

#define USER686 ((1 << X86_FEATURE_TSC)|\

		 (1 << X86_FEATURE_CX8)|\

		 (1 << X86_FEATURE_CMOV))

        if (c->x86 == 5 && (c->x86_capability[0] & USER686) == USER686)

		c->x86 = 6;



#ifdef CONFIG_SYSCTL

	/* randomize_va_space slows us down enormously;

	   it probably triggers retranslation of x86->native bytecode */