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Commit a755ecb2 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: Account for deviation in PLL rate configuration during voltage voting 



Fabia PLLs only have 16 bits to program the fractional divider
for the PLL. Hence, there is a difference between the desired
rate and the actual rate that the PLL is programmed to. Account
for this difference during voltage voting for these clocks.

Change-Id: I6daef37bcfd7634c452ebcd0d6fd5c108ae8e027
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 24c8b94e

drivers/clk/clk.c

+9 −1
Original line number Diff line number Diff line
@@ -483,8 +483,16 @@ static int clk_find_vdd_level(struct clk_core *clk, unsigned long rate) 
{

	int level;



	/*

	 * For certain PLLs, due to the limitation in the bits allocated for

	 * programming the fractional divider, the actual rate of the PLL will

	 * be slightly higher than the requested rate (in the order of several

	 * Hz). To accommodate this difference, convert the FMAX rate and the

	 * clock frequency to KHz and use that for deriving the voltage level.

	 */

	for (level = 0; level < clk->num_rate_max; level++)

		if (rate <= clk->rate_max[level])

		if (DIV_ROUND_CLOSEST(rate, 1000) <=

				DIV_ROUND_CLOSEST(clk->rate_max[level], 1000))

			break;



	if (level == clk->num_rate_max) {