Loading arch/arm64/boot/dts/qcom/msm8953-cdp.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -16,3 +16,61 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8953_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8953_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l12>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 133 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 133 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; arch/arm64/boot/dts/qcom/msm8953-mtp.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -16,3 +16,61 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8953_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8953_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l12>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 133 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 133 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; arch/arm64/boot/dts/qcom/msm8953-qrd.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -16,3 +16,61 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8953_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8953_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l12>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 133 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 133 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; }; arch/arm64/boot/dts/qcom/msm8953.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -1046,6 +1046,12 @@ "sdcc_ice_sec_level_irq"; interrupts = <0 312 0>, <0 313 0>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>, <&clock_gcc clk_gcc_sdcc1_ice_core_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>, <&clock_gcc clk_gcc_sdcc1_ahb_clk>; qcom,op-freq-hz = <270000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; Loading Loading @@ -1093,6 +1099,10 @@ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>, <&clock_gcc clk_gcc_sdcc1_ice_core_clk>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <270000000 160000000>; qcom,large-address-bus; Loading Loading @@ -1131,6 +1141,10 @@ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, <&clock_gcc clk_gcc_sdcc2_apps_clk>; clock-names = "iface_clk", "core_clk"; qcom,large-address-bus; status = "disabled"; }; Loading Loading
arch/arm64/boot/dts/qcom/msm8953-cdp.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -16,3 +16,61 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8953_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8953_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l12>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 133 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 133 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; };
arch/arm64/boot/dts/qcom/msm8953-mtp.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -16,3 +16,61 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8953_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8953_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l12>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 133 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 133 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; };
arch/arm64/boot/dts/qcom/msm8953-qrd.dtsi +58 −0 Original line number Diff line number Diff line Loading @@ -16,3 +16,61 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; &sdhc_1 { /* device core power supply */ vdd-supply = <&pm8953_l8>; qcom,vdd-voltage-level = <2900000 2900000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l5>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; qcom,vdd-io-current-level = <200 325000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; status = "ok"; }; &sdhc_2 { /* device core power supply */ vdd-supply = <&pm8953_l11>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <15000 800000>; /* device communication power supply */ vdd-io-supply = <&pm8953_l12>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; #address-cells = <0>; interrupt-parent = <&sdhc_2>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 125 0 1 &intc 0 221 0 2 &tlmm 133 0>; interrupt-names = "hc_irq", "pwr_irq", "status_irq"; cd-gpios = <&tlmm 133 0x1>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; status = "ok"; };
arch/arm64/boot/dts/qcom/msm8953.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -1046,6 +1046,12 @@ "sdcc_ice_sec_level_irq"; interrupts = <0 312 0>, <0 313 0>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>, <&clock_gcc clk_gcc_sdcc1_ice_core_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>, <&clock_gcc clk_gcc_sdcc1_ahb_clk>; qcom,op-freq-hz = <270000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; Loading Loading @@ -1093,6 +1099,10 @@ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>, <&clock_gcc clk_gcc_sdcc1_ice_core_clk>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <270000000 160000000>; qcom,large-address-bus; Loading Loading @@ -1131,6 +1141,10 @@ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, <&clock_gcc clk_gcc_sdcc2_apps_clk>; clock-names = "iface_clk", "core_clk"; qcom,large-address-bus; status = "disabled"; }; Loading