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Commit a6fc9d19 authored by Philipp Zabel's avatar Philipp Zabel Committed by Shawn Guo
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ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DL 



i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 9fe595be

arch/arm/mach-imx/clk-imx6q.c

+1 −1
Original line number Diff line number Diff line
@@ -554,7 +554,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);

	clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);



	if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {

	if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {

		clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);

		clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);

	}