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Commit a69ba629 authored by Jayachandran C's avatar Jayachandran C Committed by John Crispin
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MIPS: Netlogic: Split XLP L1 i-cache among threads 



Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/


Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent a264b5e8

arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define CPU_BLOCKID_FPU		9

#define CPU_BLOCKID_MAP		10



#define ICU_DEFEATURE		0x100



#define LSU_DEFEATURE		0x304

#define LSU_DEBUG_ADDR		0x305

#define LSU_DEBUG_DATA0		0x306

arch/mips/netlogic/common/smpboot.S

+6 −0
Original line number Diff line number Diff line
@@ -69,6 +69,12 @@ 
#endif

	mtcr	t1, t0



	li	t0, ICU_DEFEATURE

	mfcr	t1, t0

	ori	t1, 0x1000	/* Enable Icache partitioning */

	mtcr	t1, t0





#ifdef XLP_AX_WORKAROUND

	li	t0, SCHED_DEFEATURE

	lui	t1, 0x0100	/* Disable BRU accepting ALU ops */