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Commit a6830095 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
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arm64: Fix mismatched cache line size detection 



commit 4c4a39dd5fe2d13e2d2fa5fceb8ef95d19fc389a upstream.

If there is a mismatch in the I/D min line size, we must
always use the system wide safe value both in applications
and in the kernel, while performing cache operations. However,
we have been checking more bits than just the min line sizes,
which triggers false negatives. We may need to trap the user
accesses in such cases, but not necessarily patch the kernel.

This patch fixes the check to do the right thing as advertised.
A new capability will be added to check mismatches in other
fields and ensure we trap the CTR accesses.

Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
Cc: <stable@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d92fa5e1

arch/arm64/include/asm/cachetype.h

+5 −0
Original line number Diff line number Diff line
@@ -22,6 +22,11 @@ 
#define CTR_L1IP_MASK		3

#define CTR_CWG_SHIFT		24

#define CTR_CWG_MASK		15

#define CTR_DMINLINE_SHIFT	16

#define CTR_IMINLINE_SHIFT	0



#define CTR_CACHE_MINLINE_MASK	\

	((0xf << CTR_DMINLINE_SHIFT) | (0xf << CTR_IMINLINE_SHIFT))



#define ICACHE_POLICY_RESERVED	0

#define ICACHE_POLICY_AIVIVT	1

arch/arm64/kernel/cpu_errata.c

+5 −2
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
 */



#include <linux/types.h>

#include <asm/cachetype.h>

#include <asm/cpu.h>

#include <asm/cputype.h>

#include <asm/cpufeature.h>
@@ -34,9 +35,11 @@ static bool 
has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,

				int scope)

{

	u64 mask = CTR_CACHE_MINLINE_MASK;



	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=

		(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);

	return (read_cpuid_cachetype() & mask) !=

	       (arm64_ftr_reg_ctrel0.sys_val & mask);

}



static int cpu_enable_trap_ctr_access(void *__unused)

arch/arm64/kernel/cpufeature.c

+2 −2
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ static const struct arm64_ftr_bits ftr_ctr[] = { 
	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),

	ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),	/* CWG */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),	/* ERG */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),	/* DminLine */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),

	/*

	 * Linux can handle differing I-cache policies. Userspace JITs will

	 * make use of *minLine.
@@ -160,7 +160,7 @@ static const struct arm64_ftr_bits ftr_ctr[] = { 
	 */

	ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_AIVIVT),	/* L1Ip */

	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0),	/* RAZ */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),	/* IminLine */

	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),

	ARM64_FTR_END,

};