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Commit a665d30f authored by Sylwester Nawrocki's avatar Sylwester Nawrocki
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clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks 



This corrects assignment of bit offsets of the MUX_SEL_CAM04 register
to the respective mux clocks.

Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 3c30e382

drivers/clk/samsung/clk-exynos5433.c

+6 −6
Original line number Diff line number Diff line
@@ -4753,21 +4753,21 @@ static struct samsung_mux_clock cam0_mux_clks[] __initdata = { 
	MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",

			mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),

	MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",

			mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1),

			mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),

	MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",

			mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1),

			mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),

	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",

			mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1),

			mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),

	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",

			mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1),

			mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),

	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,

			"mout_sclk_pixelasync_lite_c_init_b",

			mout_sclk_pixelasync_lite_c_init_b_p,

			MUX_SEL_CAM04, 24, 1),

			MUX_SEL_CAM04, 4, 1),

	MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,

			"mout_sclk_pixelasync_lite_c_init_a",

			mout_sclk_pixelasync_lite_c_init_a_p,

			MUX_SEL_CAM04, 24, 1),

			MUX_SEL_CAM04, 0, 1),

};



static struct samsung_div_clock cam0_div_clks[] __initdata = {