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Commit a62eb059 authored by Ramprasad Katkam's avatar Ramprasad Katkam Committed by Banajit Goswami
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ASoC: sdm660_cdc: Add writeable registers for Dig_cdc and sdw codec regmap 



Add Writeable registers list for Digital codec and soundwire codec
regmap config to avoid invalid register access during reg_cache_sync.
Ensure digital codec clock is enabled before regcache sync to avoid
AHB access errors.Modify mutex use to avoid clock disabling during
regmap register access.

Change-Id: I8ab84f80298e01d145395f1347352afe5cfbcc9e
Signed-off-by: default avatarRamprasad Katkam <katkam@codeaurora.org>
parent d60179ab

sound/soc/codecs/msm_sdw/msm-sdw-tables.c

+97 −0
Original line number Diff line number Diff line
@@ -220,3 +220,100 @@ const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER] = { 
	[MSM_SDW_TOP_I2S_RESET] = 1,

	[MSM_SDW_TOP_BLOCKS_RESET] = 1,

};



const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER] = {

	[MSM_SDW_PAGE_REGISTER] = 1,

	[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1,

	[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1,

	[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1,

	[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1,

	[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1,

	[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1,

	[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1,

	[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1,

	[MSM_SDW_COMPANDER7_CTL0] = 1,

	[MSM_SDW_COMPANDER7_CTL1] = 1,

	[MSM_SDW_COMPANDER7_CTL2] = 1,

	[MSM_SDW_COMPANDER7_CTL3] = 1,

	[MSM_SDW_COMPANDER7_CTL4] = 1,

	[MSM_SDW_COMPANDER7_CTL5] = 1,

	[MSM_SDW_COMPANDER7_CTL7] = 1,

	[MSM_SDW_COMPANDER8_CTL0] = 1,

	[MSM_SDW_COMPANDER8_CTL1] = 1,

	[MSM_SDW_COMPANDER8_CTL2] = 1,

	[MSM_SDW_COMPANDER8_CTL3] = 1,

	[MSM_SDW_COMPANDER8_CTL4] = 1,

	[MSM_SDW_COMPANDER8_CTL5] = 1,

	[MSM_SDW_COMPANDER8_CTL7] = 1,

	[MSM_SDW_RX7_RX_PATH_CTL] = 1,

	[MSM_SDW_RX7_RX_PATH_CFG0] = 1,

	[MSM_SDW_RX7_RX_PATH_CFG1] = 1,

	[MSM_SDW_RX7_RX_PATH_CFG2] = 1,

	[MSM_SDW_RX7_RX_VOL_CTL] = 1,

	[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1,

	[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1,

	[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC0] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC1] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC2] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC3] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC5] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC6] = 1,

	[MSM_SDW_RX7_RX_PATH_SEC7] = 1,

	[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1,

	[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1,

	[MSM_SDW_RX8_RX_PATH_CTL] = 1,

	[MSM_SDW_RX8_RX_PATH_CFG0] = 1,

	[MSM_SDW_RX8_RX_PATH_CFG1] = 1,

	[MSM_SDW_RX8_RX_PATH_CFG2] = 1,

	[MSM_SDW_RX8_RX_VOL_CTL] = 1,

	[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1,

	[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1,

	[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC0] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC1] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC2] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC3] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC5] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC6] = 1,

	[MSM_SDW_RX8_RX_PATH_SEC7] = 1,

	[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1,

	[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1,

	[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1,

	[MSM_SDW_BOOST0_BOOST_CTL] = 1,

	[MSM_SDW_BOOST0_BOOST_CFG1] = 1,

	[MSM_SDW_BOOST0_BOOST_CFG2] = 1,

	[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1,

	[MSM_SDW_BOOST1_BOOST_CTL] = 1,

	[MSM_SDW_BOOST1_BOOST_CFG1] = 1,

	[MSM_SDW_BOOST1_BOOST_CFG2] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1,

	[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1,

	[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1,

	[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1,

	[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1,

	[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1,

	[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1,

	[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1,

	[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1,

	[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1,

	[MSM_SDW_TOP_TOP_CFG0] = 1,

	[MSM_SDW_TOP_TOP_CFG1] = 1,

	[MSM_SDW_TOP_RX_I2S_CTL] = 1,

	[MSM_SDW_TOP_TX_I2S_CTL] = 1,

	[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1,

	[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1,

	[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1,

	[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1,

	[MSM_SDW_TOP_FREQ_MCLK] = 1,

	[MSM_SDW_TOP_DEBUG_BUS_SEL] = 1,

	[MSM_SDW_TOP_DEBUG_EN] = 1,

	[MSM_SDW_TOP_I2S_RESET] = 1,

	[MSM_SDW_TOP_BLOCKS_RESET] = 1,

};

sound/soc/codecs/msm_sdw/msm_sdw.h

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
extern const struct regmap_config msm_sdw_regmap_config;

extern const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER];

extern const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER];

extern const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER];



enum {

	MSM_SDW_RX4 = 0,

sound/soc/codecs/msm_sdw/msm_sdw_regmap.c

+6 −0
Original line number Diff line number Diff line
@@ -115,6 +115,11 @@ static bool msm_sdw_is_readable_register(struct device *dev, unsigned int reg) 
	return msm_sdw_reg_readable[reg];

}



static bool msm_sdw_is_writeable_register(struct device *dev, unsigned int reg)

{

	return msm_sdw_reg_writeable[reg];

}



static bool msm_sdw_is_volatile_register(struct device *dev, unsigned int reg)

{

	switch (reg) {
@@ -150,6 +155,7 @@ const struct regmap_config msm_sdw_regmap_config = { 
	.reg_defaults = msm_sdw_defaults,

	.num_reg_defaults = ARRAY_SIZE(msm_sdw_defaults),

	.max_register = MSM_SDW_MAX_REGISTER,

	.writeable_reg = msm_sdw_is_writeable_register,

	.volatile_reg = msm_sdw_is_volatile_register,

	.readable_reg = msm_sdw_is_readable_register,

};

sound/soc/codecs/sdm660_cdc/msm-cdc-common.h

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ extern struct reg_default 
		msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE];



bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg);

bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg);

bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg);



enum {

sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c

+26 −3
Original line number Diff line number Diff line
@@ -77,8 +77,8 @@ static int msm_digcdc_clock_control(bool flag) 


	pdata = snd_soc_card_get_drvdata(registered_digcodec->component.card);



	mutex_lock(&pdata->cdc_int_mclk0_mutex);

	if (flag) {

		mutex_lock(&pdata->cdc_int_mclk0_mutex);

		if (atomic_read(&pdata->int_mclk0_enabled) == false) {

			pdata->digital_cdc_core_clk.enable = 1;

			ret = afe_set_lpass_clock_v2(
@@ -93,7 +93,6 @@ static int msm_digcdc_clock_control(bool flag) 
				 */

				if (ret == -ENODEV)

					msm_dig_cdc->regmap->cache_only = true;

				mutex_unlock(&pdata->cdc_int_mclk0_mutex);

				return ret;

			}

			pr_debug("enabled digital codec core clk\n");
@@ -102,10 +101,10 @@ static int msm_digcdc_clock_control(bool flag) 
					      50);

		}

	} else {

		mutex_unlock(&pdata->cdc_int_mclk0_mutex);

		dev_dbg(registered_digcodec->dev,

			"disable MCLK, workq to disable set already\n");

	}

	mutex_unlock(&pdata->cdc_int_mclk0_mutex);

	return 0;

}
@@ -116,6 +115,7 @@ static void enable_digital_callback(void *flag) 


static void disable_digital_callback(void *flag)

{

	msm_digcdc_clock_control(false);

	pr_debug("disable mclk happens in workq\n");

}
@@ -982,6 +982,7 @@ static int msm_dig_cdc_event_notify(struct notifier_block *block, 
	struct snd_soc_codec *codec = registered_digcodec;

	struct msm_dig_priv *msm_dig_cdc = snd_soc_codec_get_drvdata(codec);

	struct msm_asoc_mach_data *pdata = NULL;

	int ret = -EINVAL;



	pdata = snd_soc_card_get_drvdata(codec->component.card);
@@ -1073,7 +1074,28 @@ static int msm_dig_cdc_event_notify(struct notifier_block *block, 
	case DIG_CDC_EVENT_SSR_UP:

		regcache_cache_only(msm_dig_cdc->regmap, false);

		regcache_mark_dirty(msm_dig_cdc->regmap);



		mutex_lock(&pdata->cdc_int_mclk0_mutex);

		pdata->digital_cdc_core_clk.enable = 1;

		ret = afe_set_lpass_clock_v2(

					AFE_PORT_ID_INT0_MI2S_RX,

					&pdata->digital_cdc_core_clk);

		if (ret < 0) {

			pr_err("%s:failed to enable the MCLK\n",

			       __func__);

			mutex_unlock(&pdata->cdc_int_mclk0_mutex);

			break;

		}

		mutex_unlock(&pdata->cdc_int_mclk0_mutex);



		regcache_sync(msm_dig_cdc->regmap);



		mutex_lock(&pdata->cdc_int_mclk0_mutex);

		pdata->digital_cdc_core_clk.enable = 0;

		afe_set_lpass_clock_v2(

				AFE_PORT_ID_INT0_MI2S_RX,

				&pdata->digital_cdc_core_clk);

		mutex_unlock(&pdata->cdc_int_mclk0_mutex);

		break;

	case DIG_CDC_EVENT_INVALID:

	default:
@@ -2033,6 +2055,7 @@ const struct regmap_config msm_digital_regmap_config = { 
	.cache_type = REGCACHE_FLAT,

	.reg_defaults = msm89xx_cdc_core_defaults,

	.num_reg_defaults = MSM89XX_CDC_CORE_MAX_REGISTER,

	.writeable_reg = msm89xx_cdc_core_writeable_reg,

	.readable_reg = msm89xx_cdc_core_readable_reg,

	.volatile_reg = msm89xx_cdc_core_volatile_reg,

	.reg_format_endian = REGMAP_ENDIAN_NATIVE,