Loading arch/arm64/boot/dts/qcom/sdm845-camera.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -28,7 +28,7 @@ gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&pm8998_l26>; mipi-csi-vdd-supply = <&pm8998_l1>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, Loading Loading @@ -62,7 +62,7 @@ gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&pm8998_l26>; mipi-csi-vdd-supply = <&pm8998_l1>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, Loading Loading @@ -97,7 +97,7 @@ gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&pm8998_l26>; mipi-csi-vdd-supply = <&pm8998_l1>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, Loading Loading
arch/arm64/boot/dts/qcom/sdm845-camera.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -28,7 +28,7 @@ gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&pm8998_l26>; mipi-csi-vdd-supply = <&pm8998_l1>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, Loading Loading @@ -62,7 +62,7 @@ gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&pm8998_l26>; mipi-csi-vdd-supply = <&pm8998_l1>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, Loading Loading @@ -97,7 +97,7 @@ gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&pm8998_l26>; mipi-csi-vdd-supply = <&pm8998_l1>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, Loading