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Commit a5cf9e24 authored by Stuart Menefy's avatar Stuart Menefy Committed by Paul Mundt
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sh: Improve comments int SH4 cache flushing code 



This is a pure documentation, to try to explain why the cache flushing code
for the SH4 is implemented the way it is.

Signed-off-by: default avatarStuart Menefy <stuart.menefy@st.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 5e9377ec

arch/sh/mm/cache-sh4.c

+11 −0
Original line number Original line Diff line number Diff line
@@ -581,6 +581,17 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys, 
 * Break the 1, 2 and 4 way variants of this out into separate functions to

 * Break the 1, 2 and 4 way variants of this out into separate functions to

 * avoid nearly all the overhead of having the conditional stuff in the function

 * avoid nearly all the overhead of having the conditional stuff in the function

 * bodies (+ the 1 and 2 way cases avoid saving any registers too).

 * bodies (+ the 1 and 2 way cases avoid saving any registers too).

 *

 * We want to eliminate unnecessary bus transactions, so this code uses

 * a non-obvious technique.

 *

 * Loop over a cache way sized block of, one cache line at a time. For each

 * line, use movca.a to cause the current cache line contents to be written

 * back, but without reading anything from main memory. However this has the

 * side effect that the cache is now caching that memory location. So follow

 * this with a cache invalidate to mark the cache line invalid. And do all

 * this with interrupts disabled, to avoid the cache line being accidently

 * evicted while it is holding garbage.

 */

 */

static void __flush_dcache_segment_1way(unsigned long start,

static void __flush_dcache_segment_1way(unsigned long start,

					unsigned long extent_per_way)

					unsigned long extent_per_way)