Merge "thermal: qpnp-adc-tm: Update adc_tm register offsets for PMIC5" (a5c3d38a) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@ VADC node
		Required properties:
		- compatible : should be "qcom,qpnp-vadc" for Voltage ADC device driver and
		"qcom,qpnp-vadc-hc" for VADC_HC voltage ADC device driver.
		should include "qcom,qpnp-adc-hc-pm5" for PMIC5.
		- reg : offset and length of the PMIC Aribter register map.
		- address-cells : Must be one.
		- size-cells : Must be zero.

Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@ VADC_TM node
		Required properties:
		- compatible : should be "qcom,qpnp-adc-tm-hc" for thermal ADC driver using
		refreshed BTM peripheral.
		should include "qcom,qpnp-adc-tm-hc-pm5" for PMIC5.
		- reg : offset and length of the PMIC Aribter register map.
		- address-cells : Must be one.
		- size-cells : Must be zero.

drivers/hwmon/qpnp-adc-common.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -2495,6 +2495,12 @@ int32_t qpnp_adc_get_devicetree_data(struct platform_device *pdev,
		}
		}

		if (of_device_is_compatible(node, "qcom,qpnp-adc-hc-pm5") \|\|
		of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc-pm5"))
		adc_prop->is_pmic_5 = true;
		else
		adc_prop->is_pmic_5 = false;

		for_each_child_of_node(node, child) {
		int channel_num, scaling = 0, post_scaling = 0;
		int fast_avg_setup, calib_type = 0, rc, hw_settle_time = 0;

drivers/hwmon/qpnp-adc-voltage.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -35,8 +35,6 @@
		#include <linux/power_supply.h>
		#include <linux/thermal.h>

		#define QPNP_VADC_HC_VREF_CODE 0x4000

		/* QPNP VADC register definition */
		#define QPNP_VADC_REVISION1 0x0
		#define QPNP_VADC_REVISION2 0x1
		@@ -508,7 +506,7 @@ int32_t qpnp_vadc_hc_read(struct qpnp_vadc_chip *vadc,
		goto fail_unlock;
		}

		if (vadc->adc->adc_prop->full_scale_code == QPNP_VADC_HC_VREF_CODE) {
		if (!vadc->adc->adc_prop->is_pmic_5) {
		if (!vadc->vadc_init_calib) {
		rc = qpnp_vadc_calib_device(vadc);
		if (rc) {
		@@ -2595,6 +2593,8 @@ static const struct of_device_id qpnp_vadc_match_table[] = {
		},
		{ .compatible = "qcom,qpnp-vadc-hc",
		},
		{ .compatible = "qcom,qpnp-adc-hc-pm5",
		},
		{}
		};

drivers/thermal/qpnp-adc-tm.c

+54 −18

Original line number	Diff line number	Diff line
		@@ -191,6 +191,8 @@

		#define QPNP_BTM_MEAS_INTERVAL_CTL 0x50
		#define QPNP_BTM_MEAS_INTERVAL_CTL2 0x51
		#define QPNP_BTM_MEAS_INTERVAL_CTL_PM5 0x44
		#define QPNP_BTM_MEAS_INTERVAL_CTL2_PM5 0x45
		#define QPNP_ADC_TM_MEAS_INTERVAL_TIME_SHIFT 0x3
		#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT 0x4
		#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK 0xf0
		@@ -742,6 +744,7 @@ static int32_t qpnp_adc_tm_timer_interval_select(
		bool chan_found = false;
		u8 meas_interval_timer2 = 0, timer_interval_store = 0;
		uint32_t btm_chan_idx = 0;
		bool is_pmic_5 = chip->adc->adc_prop->is_pmic_5;

		while (i < chip->max_channels_available) {
		if (chip->sensor[i].btm_channel_num == btm_chan) {
		@@ -763,10 +766,18 @@ static int32_t qpnp_adc_tm_timer_interval_select(
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_ADC_TM_MEAS_INTERVAL_CTL,
		chip->sensor[chan_idx].meas_interval, 1);
		else
		else {
		if (!is_pmic_5)
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL,
		chip->sensor[chan_idx].meas_interval, 1);
		chip->sensor[chan_idx].meas_interval,
		1);
		else
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL_PM5,
		chip->sensor[chan_idx].meas_interval,
		1);
		}
		if (rc < 0) {
		pr_err("timer1 configure failed\n");
		return rc;
		@@ -778,10 +789,16 @@ static int32_t qpnp_adc_tm_timer_interval_select(
		rc = qpnp_adc_tm_read_reg(chip,
		QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
		&meas_interval_timer2, 1);
		else
		else {
		if (!is_pmic_5)
		rc = qpnp_adc_tm_read_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2,
		&meas_interval_timer2, 1);
		else
		rc = qpnp_adc_tm_read_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
		&meas_interval_timer2, 1);
		}
		if (rc < 0) {
		pr_err("timer2 configure read failed\n");
		return rc;
		@@ -794,10 +811,16 @@ static int32_t qpnp_adc_tm_timer_interval_select(
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
		meas_interval_timer2, 1);
		else
		else {
		if (!is_pmic_5)
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2,
		meas_interval_timer2, 1);
		else
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
		meas_interval_timer2, 1);
		}
		if (rc < 0) {
		pr_err("timer2 configure failed\n");
		return rc;
		@@ -808,10 +831,16 @@ static int32_t qpnp_adc_tm_timer_interval_select(
		rc = qpnp_adc_tm_read_reg(chip,
		QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
		&meas_interval_timer2, 1);
		else
		else {
		if (!is_pmic_5)
		rc = qpnp_adc_tm_read_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2,
		&meas_interval_timer2, 1);
		else
		rc = qpnp_adc_tm_read_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
		&meas_interval_timer2, 1);
		}
		if (rc < 0) {
		pr_err("timer3 read failed\n");
		return rc;
		@@ -823,10 +852,16 @@ static int32_t qpnp_adc_tm_timer_interval_select(
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
		meas_interval_timer2, 1);
		else
		else {
		if (!is_pmic_5)
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2,
		meas_interval_timer2, 1);
		else
		rc = qpnp_adc_tm_write_reg(chip,
		QPNP_BTM_MEAS_INTERVAL_CTL2_PM5,
		meas_interval_timer2, 1);
		}
		if (rc < 0) {
		pr_err("timer3 configure failed\n");
		return rc;
		@@ -2997,6 +3032,7 @@ static int qpnp_adc_tm_initial_setup(struct qpnp_adc_tm_chip *chip)
		static const struct of_device_id qpnp_adc_tm_match_table[] = {
		{ .compatible = "qcom,qpnp-adc-tm" },
		{ .compatible = "qcom,qpnp-adc-tm-hc" },
		{ .compatible = "qcom,qpnp-adc-tm-hc-pm5" },
		{}
		};