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Commit a53485d7 authored by Jishnu Prakash's avatar Jishnu Prakash
Browse files

hwmon: qpnp-adc: Update logic to support PMIC5 



Few registers are not supported on PMIC5 which are available
on PMIC4. Update logic to program only available registers
for PMIC5.

Change-Id: I14ab3f1ebbc663f092982b95b595ec1ad08f9981
Signed-off-by: default avatarJishnu Prakash <jprakash@codeaurora.org>
parent 513494c8

drivers/hwmon/qpnp-adc-voltage.c

+2 −62
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ 
#define QPNP_VADC_CONV_TIME_MIN					1000

#define QPNP_VADC_CONV_TIME_MAX					1100

#define QPNP_ADC_COMPLETION_TIMEOUT				HZ

#define QPNP_VADC_ERR_COUNT					50

#define QPNP_VADC_ERR_COUNT					20

#define QPNP_OP_MODE_SHIFT					3



#define QPNP_VADC_THR_LSB_MASK(val)				(val & 0xff)
@@ -275,42 +275,6 @@ static int qpnp_vadc_is_valid(struct qpnp_vadc_chip *vadc) 
	return -EINVAL;

}



static int32_t qpnp_vadc_warm_rst_configure(struct qpnp_vadc_chip *vadc)

{

	int rc = 0;

	u8 data = 0, buf = 0;



	buf = QPNP_VADC_ACCESS_DATA;

	rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ACCESS, &buf, 1);

	if (rc < 0) {

		pr_err("VADC write access failed\n");

		return rc;

	}



	rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_PERH_RESET_CTL3, &data, 1);

	if (rc < 0) {

		pr_err("VADC perh reset ctl3 read failed\n");

		return rc;

	}



	buf = QPNP_VADC_ACCESS_DATA;

	rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ACCESS, &buf, 1);

	if (rc < 0) {

		pr_err("VADC write access failed\n");

		return rc;

	}



	data |= QPNP_FOLLOW_WARM_RB;



	rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_PERH_RESET_CTL3, &data, 1);

	if (rc < 0) {

		pr_err("VADC perh reset ctl3 write failed\n");

		return rc;

	}



	return 0;

}



static int32_t qpnp_vadc_mode_select(struct qpnp_vadc_chip *vadc, u8 mode_ctl)

{

	int rc;
@@ -420,20 +384,7 @@ static int qpnp_vadc_hc_check_conversion_status(struct qpnp_vadc_chip *vadc) 
static int qpnp_vadc_hc_read_data(struct qpnp_vadc_chip *vadc, int *data)

{

	int rc = 0;

	u8 buf = 0, rslt_lsb = 0, rslt_msb = 0;



	/* Set hold bit */

	rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA_HOLD_CTL, &buf, 1);

	if (rc) {

		pr_err("debug register dump failed\n");

		return rc;

	}

	buf |= QPNP_VADC_HC1_DATA_HOLD_CTL_FIELD;

	rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_DATA_HOLD_CTL, &buf, 1);

	if (rc) {

		pr_err("debug register dump failed\n");

		return rc;

	}

	u8 rslt_lsb = 0, rslt_msb = 0;



	rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA0, &rslt_lsb, 1);

	if (rc < 0) {
@@ -460,11 +411,6 @@ static int qpnp_vadc_hc_read_data(struct qpnp_vadc_chip *vadc, int *data) 
		return rc;

	}



	/* De-assert hold bit */

	buf &= ~QPNP_VADC_HC1_DATA_HOLD_CTL_FIELD;

	rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_DATA_HOLD_CTL, &buf, 1);

	if (rc)

		pr_err("de-asserting hold bit failed\n");



	return rc;

}
@@ -2753,12 +2699,6 @@ static int qpnp_vadc_probe(struct platform_device *pdev) 
		goto err_setup;

	}



	rc = qpnp_vadc_warm_rst_configure(vadc);

	if (rc < 0) {

		pr_err("Setting perp reset on warm reset failed %d\n", rc);

		goto err_setup;

	}



	INIT_WORK(&vadc->trigger_completion_work, qpnp_vadc_work);



	vadc->vadc_recalib_check = of_property_read_bool(node,