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Commit a4780b77 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Split intel_get_shared_dpll() into smaller functions 



Make the code neater by splitting the code for platforms with fixed PLL
to their own functions and splitting the logic for finding a shareable
or unused pll from the logic for setting it up.

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-4-git-send-email-ander.conselvan.de.oliveira@intel.com
parent 55be2f08

drivers/gpu/drm/i915/intel_dpll_mgr.c

+74 −35
Original line number Diff line number Diff line
@@ -145,18 +145,14 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) 
	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);

}



struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,

static enum intel_dpll_id

ibx_get_fixed_dpll(struct intel_crtc *crtc,

		   struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll;

	struct intel_shared_dpll_config *shared_dpll;

	enum intel_dpll_id i;

	int max = dev_priv->num_shared_dpll;



	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);



	if (HAS_PCH_IBX(dev_priv->dev)) {

	/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */

	i = (enum intel_dpll_id) crtc->pipe;

	pll = &dev_priv->shared_dplls[i];
@@ -164,19 +160,23 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 
	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",

		      crtc->base.base.id, pll->name);



		WARN_ON(shared_dpll[i].crtc_mask);



		goto found;

	return i;

}



	if (IS_BROXTON(dev_priv->dev)) {

		/* PLL is attached to port in bxt */

static enum intel_dpll_id

bxt_get_fixed_dpll(struct intel_crtc *crtc,

		   struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_encoder *encoder;

	struct intel_digital_port *intel_dig_port;

	struct intel_shared_dpll *pll;

	enum intel_dpll_id i;



	/* PLL is attached to port in bxt */

	encoder = intel_ddi_get_crtc_new_encoder(crtc_state);

	if (WARN_ON(!encoder))

			return NULL;

		return DPLL_ID_PRIVATE;



	intel_dig_port = enc_to_dig_port(&encoder->base);

	/* 1:1 mapping between ports and PLLs */
@@ -184,13 +184,26 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 
	pll = &dev_priv->shared_dplls[i];

	DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",

		crtc->base.base.id, pll->name);

		WARN_ON(shared_dpll[i].crtc_mask);



		goto found;

	} else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))

	return i;

}



static enum intel_dpll_id

intel_find_shared_dpll(struct intel_crtc *crtc,

		       struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

	struct intel_shared_dpll *pll;

	struct intel_shared_dpll_config *shared_dpll;

	enum intel_dpll_id i;

	int max = dev_priv->num_shared_dpll;



	if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))

		/* Do not consider SPLL */

		max = 2;



	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);



	for (i = 0; i < max; i++) {

		pll = &dev_priv->shared_dplls[i];
@@ -205,7 +218,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 
				      crtc->base.base.id, pll->name,

				      shared_dpll[i].crtc_mask,

				      pll->active);

			goto found;

			return i;

		}

	}
@@ -215,13 +228,39 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, 
		if (shared_dpll[i].crtc_mask == 0) {

			DRM_DEBUG_KMS("CRTC:%d allocated %s\n",

				      crtc->base.base.id, pll->name);

			goto found;

			return i;

		}

	}



	return DPLL_ID_PRIVATE;

}



struct intel_shared_dpll *

intel_get_shared_dpll(struct intel_crtc *crtc,

		      struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

	struct intel_shared_dpll *pll;

	struct intel_shared_dpll_config *shared_dpll;

	enum intel_dpll_id i;



	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);



	if (HAS_PCH_IBX(dev_priv->dev)) {

		i = ibx_get_fixed_dpll(crtc, crtc_state);

		WARN_ON(shared_dpll[i].crtc_mask);

	} else if (IS_BROXTON(dev_priv->dev)) {

		i = bxt_get_fixed_dpll(crtc, crtc_state);

		WARN_ON(shared_dpll[i].crtc_mask);

	} else {

		i = intel_find_shared_dpll(crtc, crtc_state);

	}



	if (i < 0)

		return NULL;



found:

	pll = &dev_priv->shared_dplls[i];



	if (shared_dpll[i].crtc_mask == 0)

		shared_dpll[i].hw_state =

			crtc_state->dpll_hw_state;