drm/radeon/cik: add rlc helpers for DPM (a412fce0) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/radeon/cik.c

+29 −0

Original line number	Diff line number	Diff line
		@@ -5587,6 +5587,35 @@ static u32 cik_halt_rlc(struct radeon_device *rdev)
		return orig;
		}

		void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
		{
		u32 tmp, i, mask;

		tmp = REQ \| MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
		WREG32(RLC_GPR_REG2, tmp);

		mask = GFX_POWER_STATUS \| GFX_CLOCK_STATUS;
		for (i = 0; i < rdev->usec_timeout; i++) {
		if ((RREG32(RLC_GPM_STAT) & mask) == mask)
		break;
		udelay(1);
		}

		for (i = 0; i < rdev->usec_timeout; i++) {
		if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
		break;
		udelay(1);
		}
		}

		void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
		{
		u32 tmp;

		tmp = REQ \| MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
		WREG32(RLC_GPR_REG2, tmp);
		}

		/**
		* cik_rlc_stop - stop the RLC ME
		*

+9 −0

Original line number	Diff line number	Diff line
		@@ -952,6 +952,8 @@

		#define RLC_GPM_STAT 0xC400
		# define RLC_GPM_BUSY (1 << 0)
		# define GFX_POWER_STATUS (1 << 1)
		# define GFX_CLOCK_STATUS (1 << 2)

		#define RLC_PG_CNTL 0xC40C
		# define GFX_PG_ENABLE (1 << 0)
		@@ -1004,6 +1006,13 @@
		#define RLC_GPM_SCRATCH_ADDR 0xC4B0
		#define RLC_GPM_SCRATCH_DATA 0xC4B4

		#define RLC_GPR_REG2 0xC4E8
		#define REQ 0x00000001
		#define MESSAGE(x) ((x) << 1)
		#define MESSAGE_MASK 0x0000001e
		#define MSG_ENTER_RLC_SAFE_MODE 1
		#define MSG_EXIT_RLC_SAFE_MODE 0

		#define CP_HPD_EOP_BASE_ADDR 0xC904
		#define CP_HPD_EOP_BASE_ADDR_HI 0xC908
		#define CP_HPD_EOP_VMID 0xC90C